diff --git a/litex/gen/fhdl/verilog.py b/litex/gen/fhdl/verilog.py
index 0e8b7d7fb..4c581d86f 100644
--- a/litex/gen/fhdl/verilog.py
+++ b/litex/gen/fhdl/verilog.py
@@ -205,7 +205,7 @@ def _printattr(attr, attr_translate):
             attr_name, attr_value = attr
         else:
             # translated attribute
-            at = attr_translate[attr]
+            at = attr_translate.get(attr, None)
             if at is None:
                 continue
             attr_name, attr_value = at