From 4e15fd54b02cd93783e962c0db5680baa0d34ff9 Mon Sep 17 00:00:00 2001
From: bunnie <bunnie@kosagi.com>
Date: Mon, 15 May 2023 18:45:10 +0800
Subject: [PATCH] add an option to generate without reg initializers (asic
 targets)

ASIC targets can't set a reg to a known value on boot, so for
more accurate simulations it would be nice to have an option
in the platform to specify generating the verilog without 'reg'
initializers. The presence of these initializers can mask
problems in simulations with X-prop that can lead to missing
explicit reset conditions.
---
 litex/gen/fhdl/verilog.py | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/litex/gen/fhdl/verilog.py b/litex/gen/fhdl/verilog.py
index 8a6bc4c05..48994fe1b 100644
--- a/litex/gen/fhdl/verilog.py
+++ b/litex/gen/fhdl/verilog.py
@@ -421,7 +421,7 @@ def _print_module(f, ios, name, ns, attr_translate):
 
     return r
 
-def _print_signals(f, ios, name, ns, attr_translate):
+def _print_signals(f, ios, name, ns, attr_translate, asic=False):
     sigs = list_signals(f) | list_special_ios(f, ins=True, outs=True, inouts=True)
     special_outs = list_special_ios(f, ins=False, outs=True,  inouts=True)
     inouts       = list_special_ios(f, ins=False, outs=False, inouts=True)
@@ -434,7 +434,10 @@ def _print_signals(f, ios, name, ns, attr_translate):
         if sig in wires:
             r += "wire " + _print_signal(ns, sig) + ";\n"
         else:
-            r += "reg  " + _print_signal(ns, sig) + " = " + _print_expression(ns, sig.reset)[0] + ";\n"
+            if asic:
+                r += "reg  " + _print_signal(ns, sig) + ";\n"  # ASICs can't assign an initial value to a reg, it is always X
+            else:
+                r += "reg  " + _print_signal(ns, sig) + " = " + _print_expression(ns, sig.reset)[0] + ";\n"
     return r
 
 # ------------------------------------------------------------------------------------------------ #
@@ -532,6 +535,8 @@ def convert(f, ios=set(), name="top", platform=None,
     # Sim parameters.
     time_unit      = "1ns",
     time_precision = "1ps",
+    # Generate for ASIC simulation (i.e. capture X-on-init for regs)
+    asic = False,
     ):
 
     # Build Logic.
@@ -618,7 +623,7 @@ def convert(f, ios=set(), name="top", platform=None,
 
     # Module Signals.
     verilog += _print_separator("Signals")
-    verilog += _print_signals(f, ios, name, ns, attr_translate)
+    verilog += _print_signals(f, ios, name, ns, attr_translate, asic)
 
     # Combinatorial Logic.
     verilog += _print_separator("Combinatorial Logic")