From 4dae3a9f4da14aa602ffda87ac4c3d2682577ba1 Mon Sep 17 00:00:00 2001 From: Andrew Dennison Date: Mon, 29 Jan 2024 16:19:44 +1100 Subject: [PATCH 1/9] build/openfpgaloader: report command line on error Helps explain failures --- litex/build/openfpgaloader.py | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/litex/build/openfpgaloader.py b/litex/build/openfpgaloader.py index 8721dcfb9..21e704bf4 100644 --- a/litex/build/openfpgaloader.py +++ b/litex/build/openfpgaloader.py @@ -71,4 +71,8 @@ class OpenFPGALoader(GenericProgrammer): cmd.append(str(value)) # Execute Command. - self.call(cmd) + try: + self.call(cmd) + except OSError as e: + print(' '.join(cmd)) + raise From 08189663ba5e568d1667c8743af98adda4839e8e Mon Sep 17 00:00:00 2001 From: Andrew Dennison Date: Tue, 30 Jan 2024 17:15:45 +1100 Subject: [PATCH 2/9] soc/add_spi_flash: fix bios 1x mode support require both phy and flash support to enable QUAD/QPI capability. Many flash devices support 4x read but may be on a 1x phy --- litex/soc/integration/soc.py | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 442ba3176..385e83da1 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -1909,10 +1909,11 @@ class LiteXSoC(SoC): self.add_constant(f"{name}_MODULE_NAME", module.name.upper()) self.add_constant(f"{name}_MODULE_TOTAL_SIZE", module.total_size) self.add_constant(f"{name}_MODULE_PAGE_SIZE", module.page_size) - if SpiNorFlashOpCodes.READ_1_1_4 in module.supported_opcodes: - self.add_constant(f"{name}_MODULE_QUAD_CAPABLE") - if SpiNorFlashOpCodes.READ_4_4_4 in module.supported_opcodes: - self.add_constant(f"{name}_MODULE_QPI_CAPABLE") + if mode in [ "4x" ]: + if SpiNorFlashOpCodes.READ_1_1_4 in module.supported_opcodes: + self.add_constant(f"{name}_MODULE_QUAD_CAPABLE") + if SpiNorFlashOpCodes.READ_4_4_4 in module.supported_opcodes: + self.add_constant(f"{name}_MODULE_QPI_CAPABLE") if software_debug: self.add_constant(f"{name}_DEBUG") From 1dddfa6841f9e40914f735d8d589d171096a24c0 Mon Sep 17 00:00:00 2001 From: Andrew Dennison Date: Thu, 1 Feb 2024 09:57:51 +1100 Subject: [PATCH 3/9] soc/add_spi_flash: fix default divisor and PHY_CLOCK calculation Ensure default_divisor is set to desired default - 1 as required by LiteSPIClkGen Calculate actual PHY_CLK based on default_divisor --- litex/soc/integration/soc.py | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 385e83da1..1031c43be 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -1884,17 +1884,21 @@ class LiteXSoC(SoC): from litespi import LiteSPI from litespi.phy.generic import LiteSPIPHY from litespi.opcodes import SpiNorFlashOpCodes + import math # Checks/Parameters. assert mode in ["1x", "4x"] if clk_freq is None: clk_freq = self.sys_clk_freq + # From LiteSPIClkGen: clk_freq will be ``sys_clk_freq/(2*(1+div))``. + default_divisor = math.ceil(self.sys_clk_freq/(clk_freq*2))-1 + clk_freq = int(self.sys_clk_freq/(2*(1+default_divisor))) # PHY. spiflash_phy = phy if spiflash_phy is None: self.check_if_exists(f"{name}_phy") spiflash_pads = self.platform.request(name if mode == "1x" else name + mode) - spiflash_phy = LiteSPIPHY(spiflash_pads, module, device=self.platform.device, default_divisor=int(self.sys_clk_freq/clk_freq), rate=rate) + spiflash_phy = LiteSPIPHY(spiflash_pads, module, device=self.platform.device, default_divisor=default_divisor, rate=rate) self.add_module(name=f"{name}_phy", module=spiflash_phy) # Core. From 51c3cb3552a8770c817ead7c1e87d477f384effb Mon Sep 17 00:00:00 2001 From: Andrew Dennison Date: Thu, 1 Feb 2024 10:01:15 +1100 Subject: [PATCH 4/9] soc/add_spi_flash: default clk_freq to 20MHz This is safer than defaulting to sys_clock / 2 if sys_clock > 100MHz clk_freq tuning will result in a faster clock if supported by hardware. --- litex/soc/integration/soc.py | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 1031c43be..16fba83ab 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -1879,7 +1879,7 @@ class LiteXSoC(SoC): self.add_constant("ETH_PHY_NO_RESET") # Disable reset from BIOS to avoid disabling Hardware Interface. # Add SPI Flash -------------------------------------------------------------------------------- - def add_spi_flash(self, name="spiflash", mode="4x", clk_freq=None, module=None, phy=None, rate="1:1", software_debug=False, **kwargs): + def add_spi_flash(self, name="spiflash", mode="4x", clk_freq=20e6, module=None, phy=None, rate="1:1", software_debug=False, **kwargs): # Imports. from litespi import LiteSPI from litespi.phy.generic import LiteSPIPHY @@ -1888,7 +1888,6 @@ class LiteXSoC(SoC): # Checks/Parameters. assert mode in ["1x", "4x"] - if clk_freq is None: clk_freq = self.sys_clk_freq # From LiteSPIClkGen: clk_freq will be ``sys_clk_freq/(2*(1+div))``. default_divisor = math.ceil(self.sys_clk_freq/(clk_freq*2))-1 clk_freq = int(self.sys_clk_freq/(2*(1+default_divisor))) From e0416639f762b4035e22b98ed61cb7fe713c2b7c Mon Sep 17 00:00:00 2001 From: Andrew Dennison Date: Thu, 1 Feb 2024 10:09:06 +1100 Subject: [PATCH 5/9] software/liblitespi/spiflash: fix reported flash clk --- litex/soc/software/liblitespi/spiflash.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litex/soc/software/liblitespi/spiflash.c b/litex/soc/software/liblitespi/spiflash.c index 410c43948..e31f21410 100644 --- a/litex/soc/software/liblitespi/spiflash.c +++ b/litex/soc/software/liblitespi/spiflash.c @@ -46,13 +46,13 @@ int spiflash_freq_init(void) #endif } lowest_div++; - printf("SPI Flash clk configured to %d MHz\n", (SPIFLASH_PHY_FREQUENCY/(2*(1 + lowest_div)))/1000000); + printf("SPI Flash clk configured to %d MHz\n", CONFIG_CLOCK_FREQUENCY/(2*(1+lowest_div)*1000000)); spiflash_phy_clk_divisor_write(lowest_div); #else - printf("SPI Flash clk configured to %ld MHz\n", (unsigned long)(SPIFLASH_PHY_FREQUENCY/1e6)); + printf("SPI Flash clk configured to %ld MHz\n", SPIFLASH_PHY_FREQUENCY/1000000); #endif From 3a890a077b138d674f11841564db2042f6871827 Mon Sep 17 00:00:00 2001 From: Andrew Dennison Date: Thu, 1 Feb 2024 10:14:20 +1100 Subject: [PATCH 6/9] software/liblitespi/spiflash: fix clk_freq tuning with L2 cache Correct CRC was always calculated, regardless of divisor, as the test flash block was in the L2 cache. This resulted in the minimum divisor being used and incorrect flash reads with 200MHz sys_clock. --- litex/soc/software/liblitespi/spiflash.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/litex/soc/software/liblitespi/spiflash.c b/litex/soc/software/liblitespi/spiflash.c index e31f21410..987b7493e 100644 --- a/litex/soc/software/liblitespi/spiflash.c +++ b/litex/soc/software/liblitespi/spiflash.c @@ -25,6 +25,8 @@ int spiflash_freq_init(void) unsigned int lowest_div, crc, crc_test; lowest_div = spiflash_phy_clk_divisor_read(); + flush_cpu_dcache(); + flush_l2_cache(); crc = crc32((unsigned char *)SPIFLASH_BASE, SPI_FLASH_BLOCK_SIZE); crc_test = crc; @@ -40,6 +42,8 @@ int spiflash_freq_init(void) while((crc == crc_test) && (lowest_div-- > 0)) { spiflash_phy_clk_divisor_write((uint32_t)lowest_div); + flush_cpu_dcache(); + flush_l2_cache(); crc_test = crc32((unsigned char *)SPIFLASH_BASE, SPI_FLASH_BLOCK_SIZE); #ifdef SPIFLASH_DEBUG printf("[DIV: %d] %08x\n\r", lowest_div, crc_test); From de594e44c983abcb32ea56c35608dc77e293e82f Mon Sep 17 00:00:00 2001 From: Andrew Dennison Date: Thu, 1 Feb 2024 10:18:52 +1100 Subject: [PATCH 7/9] software/bios/cmds: fix crc command with L2 cache Same CRC was always reported if the memory region was in the cache... Noticed when manually testing spiflash divisor. --- litex/soc/software/bios/cmds/cmd_bios.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/litex/soc/software/bios/cmds/cmd_bios.c b/litex/soc/software/bios/cmds/cmd_bios.c index 2006dd540..5acf67140 100644 --- a/litex/soc/software/bios/cmds/cmd_bios.c +++ b/litex/soc/software/bios/cmds/cmd_bios.c @@ -115,6 +115,8 @@ static void crc_handler(int nb_params, char **params) return; } + flush_cpu_dcache(); + flush_l2_cache(); printf("CRC32: %08x", crc32((unsigned char *)addr, length)); } From afe7b939952d15672612716059b09f99edb0466e Mon Sep 17 00:00:00 2001 From: Andrew Dennison Date: Thu, 1 Feb 2024 10:22:46 +1100 Subject: [PATCH 8/9] software/liblitespi/spiflash: fix warnings --- litex/soc/software/liblitespi/spiflash.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/litex/soc/software/liblitespi/spiflash.c b/litex/soc/software/liblitespi/spiflash.c index 987b7493e..53bb936ef 100644 --- a/litex/soc/software/liblitespi/spiflash.c +++ b/litex/soc/software/liblitespi/spiflash.c @@ -1,6 +1,7 @@ // This file is Copyright (c) 2020 Antmicro // License: BSD +#include #include #include #include @@ -67,7 +68,7 @@ void spiflash_dummy_bits_setup(unsigned int dummy_bits) { spiflash_core_mmap_dummy_bits_write((uint32_t)dummy_bits); #ifdef SPIFLASH_DEBUG - printf("Dummy bits set to: %d\n\r", spiflash_core_mmap_dummy_bits_read()); + printf("Dummy bits set to: %" PRIx32 "\n\r", spiflash_core_mmap_dummy_bits_read()); #endif } @@ -111,7 +112,7 @@ static uint32_t transfer_byte(uint8_t b) return spiflash_core_master_rxtx_read(); } -static void transfer_cmd(uint8_t *bs, uint8_t *resp, int len) +static void transfer_cmd(volatile uint8_t *bs, volatile uint8_t *resp, int len) { spiflash_core_master_phyconfig_len_write(8); spiflash_core_master_phyconfig_width_write(1); @@ -174,7 +175,7 @@ static void page_program(uint32_t addr, uint8_t *data, int len) w_buf[1] = addr>>16; w_buf[2] = addr>>8; w_buf[3] = addr>>0; - memcpy(w_buf+4, data, len); + memcpy((void *)w_buf+4, (void *)data, len); transfer_cmd(w_buf, r_buf, len+4); } From fc85fdd178fa6711cb9055128fdc71df9ba86dd7 Mon Sep 17 00:00:00 2001 From: Andrew Dennison Date: Thu, 1 Feb 2024 15:51:30 +1100 Subject: [PATCH 9/9] build/openfpgaloader: support args with '-' many openfpgaloader args have a name with '-' as per normal convention. This kwarg now works: file_type="raw" --- litex/build/openfpgaloader.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/build/openfpgaloader.py b/litex/build/openfpgaloader.py index 21e704bf4..8b41d3093 100644 --- a/litex/build/openfpgaloader.py +++ b/litex/build/openfpgaloader.py @@ -66,7 +66,7 @@ class OpenFPGALoader(GenericProgrammer): # Handle kwargs for specific, less common cases. for key, value in kwargs.items(): - cmd.append(f"--{key}") + cmd.append(f"--{key.replace('_', '-')}") if value is not None: cmd.append(str(value))