From be40e796f2d5b609da37cf27515db50824787930 Mon Sep 17 00:00:00 2001 From: Gabriel Somlo Date: Fri, 2 Dec 2022 10:32:35 -0500 Subject: [PATCH] integration/soc: Warn on MemBus <-> LiteDRAM AXI width conversion CPUs with a dedicated memory port (MemBus) are typically connected directly to the LiteDRAM port. Some models (e.g., Rocket) come in (otherwise equivalent) variants specifically pre-generated to fit the various "standard" LiteDRAM port widths (so far, 64, 128, or 256 bits). This patch introduces a warning when the CPU variant's dedicated MemBus doesn't exactly match the width of LiteDRAM, requiring explicit conversion. The goal is to inform the user and provide them with an opportunity to pick a more suitable CPU variant (of matching MemBus width), if available. --- litex/soc/integration/soc.py | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 8238028eb..4ffac67b5 100755 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -1529,6 +1529,10 @@ class LiteXSoC(SoC): # Check if bus is an AXI bus and connect it. if isinstance(mem_bus, axi.AXIInterface): data_width_ratio = int(port.data_width/mem_bus.data_width) + if data_width_ratio != 1: + self.logger.warning("Converting MemBus({}) data width to LiteDRAM({}).".format( + colorer(mem_bus.data_width, color="yellow"), + colorer(port.data_width, color="yellow"))) # If same data_width, connect it directly. if data_width_ratio == 1: self.submodules += LiteDRAMAXI2Native(