From bf021efa2b3019f7846dd1afa4ac577dc569df49 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 8 Dec 2011 21:15:24 +0100 Subject: [PATCH] verilog: fix unary operator conversion --- migen/fhdl/verilog.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py index 979005b17..05b231cc5 100644 --- a/migen/fhdl/verilog.py +++ b/migen/fhdl/verilog.py @@ -23,7 +23,7 @@ def _printexpr(ns, node): elif isinstance(node, Operator): arity = len(node.operands) if arity == 1: - r = self.op + _printexpr(ns, node.operands[0]) + r = node.op + _printexpr(ns, node.operands[0]) elif arity == 2: r = _printexpr(ns, node.operands[0]) + " " + node.op + " " + _printexpr(ns, node.operands[1]) else: