From 5d0c5d708834f872ac1121858842c21253f5cd12 Mon Sep 17 00:00:00 2001 From: Karol Gugala Date: Fri, 15 Jan 2021 09:28:03 +0100 Subject: [PATCH] CPU: Vex: add debug slave for dbg cpu variant Signed-off-by: Karol Gugala --- litex/soc/cores/cpu/vexriscv/core.py | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py index f0d8a98a8..c4e612e76 100644 --- a/litex/soc/cores/cpu/vexriscv/core.py +++ b/litex/soc/cores/cpu/vexriscv/core.py @@ -265,6 +265,11 @@ class VexRiscv(CPU, AutoCSR): vdir = get_data_mod("cpu", "vexriscv").data_location platform.add_source(os.path.join(vdir, cpu_filename)) + def add_soc_components(self, soc, soc_region_cls): + if "debug" in self.variant: + soc.bus.add_slave("vexriscv_debug", self.debug_bus, region=soc_region_cls(origin=0xf00f0000, size=0x100, cached=False)) + + def use_external_variant(self, variant_filename): self.external_variant = True self.platform.add_source(variant_filename)