From bf3286f564d92b03925f68d3757f182257e75131 Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Mon, 23 Oct 2023 18:31:29 +0200 Subject: [PATCH] soc/integration/soc: expose interface and endianness to target (required for hybrid etherbone) --- litex/soc/integration/soc.py | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 668d2a9ca..11c75cb8d 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -1732,7 +1732,9 @@ class LiteXSoC(SoC): udp_port = 1234, buffer_depth = 16, with_ip_broadcast = True, - with_timing_constraints = True): + with_timing_constraints = True, + interface = "crossbar", + endianness = "big"): # Imports from liteeth.core import LiteEthUDPIPCore from liteeth.frontend.etherbone import LiteEthEtherbone @@ -1751,6 +1753,8 @@ class LiteXSoC(SoC): dw = data_width, with_ip_broadcast = with_ip_broadcast, with_sys_datapath = with_sys_datapath, + interface = interface, + endianness = endianness, ) if not with_sys_datapath: # Use PHY's eth_tx/eth_rx clock domains.