diff --git a/litex/soc/cores/cpu/__init__.py b/litex/soc/cores/cpu/__init__.py
index c1f8b485c..621a6672f 100644
--- a/litex/soc/cores/cpu/__init__.py
+++ b/litex/soc/cores/cpu/__init__.py
@@ -26,6 +26,9 @@ class CPU(Module):
     def __init__(self, *args, **kwargs):
         pass
 
+    def set_reset_address(self, reset_address):
+        pass
+
 class CPUNone(CPU):
     variants             = ["standard"]
     data_width           = 32
@@ -34,7 +37,11 @@ class CPUNone(CPU):
     io_regions           = {0x00000000: 0x100000000} # origin, length
     periph_buses         = []
     memory_buses         = []
-    mem_map              = {"csr": 0x00000000, "ethmac": 0x00020000} # FIXME: remove ethmac.
+    mem_map              = {
+        "csr"      : 0x00000000,
+        "ethmac"   : 0x00020000, # FIXME: Remove.
+        "spiflash" : 0x10000000, # FIXME: Remove.
+    }
 
 CPU_GCC_TRIPLE_RISCV32 = (
     "riscv64-unknown-elf",