From c0989f65dda9e9fc6f1992d9b42876d094fb4472 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 6 Aug 2018 12:19:23 +0200 Subject: [PATCH] soc/cores/cpu: add reset signal --- litex/soc/cores/cpu/lm32/core.py | 3 ++- litex/soc/cores/cpu/mor1kx/core.py | 3 ++- litex/soc/cores/cpu/vexriscv/core.py | 3 ++- 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/litex/soc/cores/cpu/lm32/core.py b/litex/soc/cores/cpu/lm32/core.py index 2ab62c786..0d92195c9 100644 --- a/litex/soc/cores/cpu/lm32/core.py +++ b/litex/soc/cores/cpu/lm32/core.py @@ -7,6 +7,7 @@ from litex.soc.interconnect import wishbone class LM32(Module): def __init__(self, platform, eba_reset, variant=None): + self.reset = Signal() assert variant == None, "No lm32 variants currently supported." self.ibus = i = wishbone.Interface() self.dbus = d = wishbone.Interface() @@ -20,7 +21,7 @@ class LM32(Module): p_eba_reset=Instance.PreformattedParam("32'h{:08x}".format(eba_reset)), i_clk_i=ClockSignal(), - i_rst_i=ResetSignal(), + i_rst_i=ResetSignal() | self.reset, i_interrupt=self.interrupt, diff --git a/litex/soc/cores/cpu/mor1kx/core.py b/litex/soc/cores/cpu/mor1kx/core.py index 8ce397dbd..3c7b451ad 100644 --- a/litex/soc/cores/cpu/mor1kx/core.py +++ b/litex/soc/cores/cpu/mor1kx/core.py @@ -8,6 +8,7 @@ from litex.soc.interconnect import wishbone class MOR1KX(Module): def __init__(self, platform, reset_pc, variant=None): assert variant in (None, "linux"), "Unsupported variant %s" % variant + self.reset = Signal() self.ibus = i = wishbone.Interface() self.dbus = d = wishbone.Interface() self.interrupt = Signal(32) @@ -69,7 +70,7 @@ class MOR1KX(Module): **cpu_args, i_clk=ClockSignal(), - i_rst=ResetSignal(), + i_rst=ResetSignal() | self.reset, i_irq_i=self.interrupt, diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py index b94a346d9..1fef0edc3 100644 --- a/litex/soc/cores/cpu/vexriscv/core.py +++ b/litex/soc/cores/cpu/vexriscv/core.py @@ -8,6 +8,7 @@ from litex.soc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage class VexRiscv(Module, AutoCSR): def __init__(self, platform, cpu_reset_address, variant=None): assert variant in (None, "debug"), "Unsupported variant %s" % variant + self.reset = Signal() self.ibus = i = wishbone.Interface() self.dbus = d = wishbone.Interface() i_err = Signal() @@ -113,7 +114,7 @@ class VexRiscv(Module, AutoCSR): **cpu_args, i_clk=ClockSignal(), - i_reset=cpu_reset, + i_reset=cpu_reset | self.reset, i_externalResetVector=cpu_reset_address, i_externalInterruptArray=self.interrupt,