From c09d57d52df4e05338de3a04bf364920d95c73e2 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 22 Aug 2024 17:36:47 +0200 Subject: [PATCH] soc/cores/hyperbus: Minor cleanups. --- litex/soc/cores/hyperbus.py | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/litex/soc/cores/hyperbus.py b/litex/soc/cores/hyperbus.py index 19a857844..e2443d90c 100644 --- a/litex/soc/cores/hyperbus.py +++ b/litex/soc/cores/hyperbus.py @@ -210,9 +210,7 @@ class HyperRAM(LiteXModule): self.sync += If(phy.shift, shift_reg_data.eq(shift_reg_data_next)) # Load. - self.sync += If(shift_reg_load, - shift_reg_data.eq(shift_reg_load_data) - ) + self.sync += If(shift_reg_load, shift_reg_data.eq(shift_reg_load_data)) # Register Access/Buffer ------------------------------------------------------------------- reg_wr_req = Signal() @@ -259,7 +257,9 @@ class HyperRAM(LiteXModule): ) ] - # Bus Latch -------------------------------------------------------------------------------- + # Bus Latch/Output ------------------------------------------------------------------------- + + # Latch. bus_adr = Signal(32) bus_we = Signal() bus_sel = Signal(4) @@ -273,6 +273,7 @@ class HyperRAM(LiteXModule): shift_reg_load.eq(1), shift_reg_load_data.eq(Cat(Signal(16), bus.dat_w)), ) + # Output. self.comb += bus.dat_r.eq(shift_reg_data_next) # FSM (Sequencer) --------------------------------------------------------------------------