From c100ef6406c04977e6d4401007ac1e414b33b739 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sun, 5 Jul 2015 22:45:53 +0200 Subject: [PATCH] liteeth/core/mac: adapt depth on AsyncFIFOs according to phy (reduce ressource usage with MII phy) --- misoclib/com/liteeth/core/mac/core/__init__.py | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/misoclib/com/liteeth/core/mac/core/__init__.py b/misoclib/com/liteeth/core/mac/core/__init__.py index f31cafa21..fdf50b803 100644 --- a/misoclib/com/liteeth/core/mac/core/__init__.py +++ b/misoclib/com/liteeth/core/mac/core/__init__.py @@ -1,6 +1,7 @@ from misoclib.com.liteeth.common import * from misoclib.com.liteeth.core.mac.core import gap, preamble, crc, padding, last_be from misoclib.com.liteeth.phy.sim import LiteEthPHYSim +from misoclib.com.liteeth.phy.mii import LiteEthPHYMII class LiteEthMACCore(Module, AutoCSR): @@ -80,8 +81,12 @@ class LiteEthMACCore(Module, AutoCSR): rx_pipeline += [rx_converter] # Cross Domain Crossing - tx_cdc = AsyncFIFO(eth_phy_description(dw), 64) - rx_cdc = AsyncFIFO(eth_phy_description(dw), 64) + if isinstance(phy, LiteEthPHYMII): + fifo_depth = 8 + else: + fifo_depth = 64 + tx_cdc = AsyncFIFO(eth_phy_description(dw), fifo_depth) + rx_cdc = AsyncFIFO(eth_phy_description(dw), fifo_depth) self.submodules += RenameClockDomains(tx_cdc, {"write": "sys", "read": "eth_tx"}) self.submodules += RenameClockDomains(rx_cdc, {"write": "eth_rx", "read": "sys"})