From 5e4a4360894352e4c0d10f8f0e118315ab20eb12 Mon Sep 17 00:00:00 2001 From: sadullah Date: Fri, 8 May 2020 02:17:37 -0400 Subject: [PATCH 1/2] Vivado Command Update for Systemverilog Add BlackParrot to LiteX setup file --- litex/build/xilinx/vivado.py | 4 +++- litex/soc/cores/cpu/blackparrot/core.py | 4 ++-- litex_setup.py | 1 + 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/litex/build/xilinx/vivado.py b/litex/build/xilinx/vivado.py index ac43dfc74..8652d7862 100644 --- a/litex/build/xilinx/vivado.py +++ b/litex/build/xilinx/vivado.py @@ -137,7 +137,9 @@ class XilinxVivadoToolchain: for filename, language, library in platform.sources: filename_tcl = "{" + filename + "}" if (language == "systemverilog"): - tcl.append("read_verilog -sv " + filename_tcl) + tcl.append("read_verilog -v " + filename_tcl) + tcl.append("set_property file_type SystemVerilog [get_files {}]" + .format(filename_tcl)) elif (language == "verilog"): tcl.append("read_verilog " + filename_tcl) elif (language == "vhdl"): diff --git a/litex/soc/cores/cpu/blackparrot/core.py b/litex/soc/cores/cpu/blackparrot/core.py index 9f3d4fb7c..296938f4a 100644 --- a/litex/soc/cores/cpu/blackparrot/core.py +++ b/litex/soc/cores/cpu/blackparrot/core.py @@ -120,7 +120,7 @@ class BlackParrotRV64(CPU): def add_sources(platform, variant="standard"): vdir = get_data_mod("cpu", "blackparrot").data_location bp_litex_dir = os.path.join(vdir,"bp_litex") - simulation = 1 + simulation = 0 if (simulation == 1): filename= os.path.join(bp_litex_dir,"flist.verilator") else: @@ -144,7 +144,7 @@ class BlackParrotRV64(CPU): a = os.popen('echo '+ str(dir_)) dir_start = a.read() vdir = dir_start[:-1]+ line[s2:-1] - platform.add_source(vdir) #this line might be changed + platform.add_source(vdir, "systemverilog") #this line might be changed elif (temp[0] == '/'): assert("No support for absolute path for now") diff --git a/litex_setup.py b/litex_setup.py index 287cc076a..bc4a98c79 100755 --- a/litex_setup.py +++ b/litex_setup.py @@ -48,6 +48,7 @@ repos = [ ("pythondata-cpu-rocket", ("https://github.com/litex-hub/", False, True)), ("pythondata-cpu-minerva", ("https://github.com/litex-hub/", False, True)), ("pythondata-cpu-microwatt", ("https://github.com/litex-hub/", False, True)), + ("pythondata-cpu-blackparrot", ("https://github.com/litex-hub/", False, True)), ] repos = OrderedDict(repos) From aed1d514ab6e11f4c023d3ba219c92cc60280c57 Mon Sep 17 00:00:00 2001 From: sadullah Date: Tue, 12 May 2020 00:58:19 -0400 Subject: [PATCH 2/2] Update README.md and core.py for BlackParrot --- .../cores/cpu/blackparrot/GETTING_STARTED.md | 24 -------- litex/soc/cores/cpu/blackparrot/README.md | 57 +++++++------------ litex/soc/cores/cpu/blackparrot/core.py | 16 ++++-- 3 files changed, 31 insertions(+), 66 deletions(-) delete mode 100644 litex/soc/cores/cpu/blackparrot/GETTING_STARTED.md diff --git a/litex/soc/cores/cpu/blackparrot/GETTING_STARTED.md b/litex/soc/cores/cpu/blackparrot/GETTING_STARTED.md deleted file mode 100644 index 55ec62e2d..000000000 --- a/litex/soc/cores/cpu/blackparrot/GETTING_STARTED.md +++ /dev/null @@ -1,24 +0,0 @@ -# Getting started (TODO:update) - -## Running BP in LiteX - -cd $LITEX/litex/tools # the folder where litex simulator resides - -./litex_sim.py --cpu-type blackparrot --cpu-variant standard --integrated-rom-size 40960 --output-dir build/BP --threads 4 --opt-level=O0 --trace --trace-start 0 - -#The above command will generate a dut.vcd file under build/BP/gateware folder. gtkwave works fine with the generated dut.vcd. - -## Additional Information - -The BlackParrot resides in $BP/pre-alpha-release/ - -core.py in $BP folder is the wrapper that integrates BP into LiteX. - -flist.verilator in $BP is all the files that litex_sim fetches for simulation. - -The top module is $BP_FPGA_DIR/ExampleBlackParrotSystem.v - -The transducer for wishbone communication is $BP_FPGA_DIR/bp2wb_convertor.v - -if args.sdram_init is not None: #instead of ram_init for sdram init boot - soc.add_constant("ROM_BOOT_ADDRESS", 0x80000000) diff --git a/litex/soc/cores/cpu/blackparrot/README.md b/litex/soc/cores/cpu/blackparrot/README.md index 4fe921f79..1fbe58365 100644 --- a/litex/soc/cores/cpu/blackparrot/README.md +++ b/litex/soc/cores/cpu/blackparrot/README.md @@ -1,60 +1,41 @@ # BlackParrot in LiteX -## Getting Started +## Prerequisites and Installing -TODO: modify getting started [Getting Started (Full)](GETTING_STARTED.md) +Please visit https://github.com/scanakci/linux-on-litex-blackparrot for the detailed setup instructions and linux boot-up process. -### Prerequisites +## Set necessary environment variables for BlackParrot + +Running BP in LiteX requires setting some environment variables. Please add the following lines to your bashrc to set them up. ``` -BP sources (https://github.com/litex-hub/pythondata-cpu-blackparrot) -RISC-V toolchain built for IA architecture (prebuilt binaries provided by LiteX works fine) -Verilator (tested with Verilator 4.031) -``` - -### Installing - -``` -https://github.com/litex-hub/pythondata-cpu-blackparrot is required to run BP in LiteX. -source ./setEnvironment.sh #should be sourced each time you open a terminal or just add this line to bashrc +pushd . +cd PATH/TO/LITEX/litex/soc/cores/cpu/blackparrot +source ./setEnvironment.sh +popd ``` ## Running BIOS +[![asciicast](https://asciinema.org/a/326077.svg)](https://asciinema.org/a/326077) + ### Simulation ``` cd $LITEX/litex/tools ./litex_sim.py --cpu-type blackparrot --cpu-variant standard --output-dir build/BP_Trial -``` -[![asciicast](https://asciinema.org/a/326077.svg)](https://asciinema.org/a/326077) - -### FPGA -``` -Coming soon! -``` - -## Running Linux - - -### Simulation -``` -Modify litex_sim.py by replacing soc.add_constant("ROM_BOOT_ADDRESS", 0x40000000) with soc.add_constant("ROM_BOOT_ADDRESS", 0x80000000) - -./litex_sim.py --cpu-type blackparrot --cpu-variant standard --integrated-rom-size 40960 --output-dir build/BP_newversion_linux_ram/ --threads 4 --ram-init build/tests/boot.bin.uart.simu.trial - -TODO: add prebuilt bbl files into python-data repository - ``` ### FPGA +Generate the bitstream 'top.bit' under build/BP_trial/gateware folder ``` -Coming soon! +$LITEX/litex/boards/genesys2.py --cpu-type blackparrot --cpu-variant standard --output-dir $PWD/build/BP_Trial --integrated-rom-size 51200 --build ``` +In another terminal, launch LiteX terminal. +``` +sudo $LITEX/litex/tools/litex_term.py /dev/ttyUSBX +``` +Load the FPGA bitstream top.bit to your FPGA (you can use vivado hardware manager) - - - - - +This step will execute LiteX BIOS. diff --git a/litex/soc/cores/cpu/blackparrot/core.py b/litex/soc/cores/cpu/blackparrot/core.py index 296938f4a..79ee294d8 100644 --- a/litex/soc/cores/cpu/blackparrot/core.py +++ b/litex/soc/cores/cpu/blackparrot/core.py @@ -29,7 +29,7 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. import os - +import sys from migen import * from litex import get_data_mod @@ -108,7 +108,15 @@ class BlackParrotRV64(CPU): ) # add verilog sources - self.add_sources(platform, variant) + try: + os.environ["BP"] + os.environ["LITEX"] + self.add_sources(platform, variant) + except KeyError: + RED = '\033[91m' + print(RED + "Please set environment variables first, refer to readme file under litex/soc/cores/cpu/blackparrot for details!") + sys.exit(1) + def set_reset_address(self, reset_address): assert not hasattr(self, "reset_address") @@ -137,14 +145,14 @@ class BlackParrotRV64(CPU): a = os.popen('echo '+ str(dir_)) dir_start = a.read() vdir = dir_start[:-1] + line[s2:-1] - platform.add_verilog_include_path(vdir) #this line might be changed + platform.add_verilog_include_path(vdir) elif (temp[0]=='$') : s2 = line.find('/') dir_ = line[0:s2] a = os.popen('echo '+ str(dir_)) dir_start = a.read() vdir = dir_start[:-1]+ line[s2:-1] - platform.add_source(vdir, "systemverilog") #this line might be changed + platform.add_source(vdir, "systemverilog") elif (temp[0] == '/'): assert("No support for absolute path for now")