From c13fe1bc63b01ea23dd658c343ae3845995d7b45 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 12 Dec 2013 17:36:17 +0100 Subject: [PATCH] specials/Memory: allow for more flexibility in memory port signals --- migen/fhdl/specials.py | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/migen/fhdl/specials.py b/migen/fhdl/specials.py index ae0a2e63b..d048e1bff 100644 --- a/migen/fhdl/specials.py +++ b/migen/fhdl/specials.py @@ -177,7 +177,10 @@ class _MemoryPort(Special): self.re = re self.we_granularity = we_granularity self.mode = mode - self.clock = ClockSignal(clock_domain) + if isinstance(clock_domain, str): + self.clock = ClockSignal(clock_domain) + else: + self.clock = clock_domain def iter_expressions(self): for attr, target_context in [ @@ -231,7 +234,11 @@ class Memory(Special): @staticmethod def emit_verilog(memory, ns): r = "" - gn = ns.get_name # usable instead of verilog_printexpr as ports contain only signals + def gn(e): + if isinstance(e, Memory): + return ns.get_name(e) + else: + return verilog_printexpr(ns, e)[0] adrbits = bits_for(memory.depth-1) r += "reg [" + str(memory.width-1) + ":0] " \