From c1871eaf42a32b4bafdc6a6383804f7a8a9e8e3b Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Sat, 9 Dec 2023 06:07:58 +0100 Subject: [PATCH] soc/integration/soc: add_jtagbone: pass address_width to UARTBone constructor --- litex/soc/integration/soc.py | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 753f9b94b..91b3b0931 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -1527,7 +1527,11 @@ class LiteXSoC(SoC): # Core. self.check_if_exists(name) jtagbone_phy = JTAGPHY(device=self.platform.device, chain=chain, platform=self.platform) - jtagbone = uart.UARTBone(phy=jtagbone_phy, clk_freq=self.sys_clk_freq) + jtagbone = uart.UARTBone( + phy = jtagbone_phy, + clk_freq = self.sys_clk_freq, + address_width = self.bus.address_width + ) self.add_module(name=f"{name}_phy", module=jtagbone_phy) self.add_module(name=name, module=jtagbone) self.bus.add_master(name=name, master=jtagbone.wishbone)