From c1eba9a6ccc0316159a5dfbefca5040afef59bcf Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 24 Nov 2017 13:16:58 +0100 Subject: [PATCH] soc/integration: add integrated_main_ram_init parameter to allow using main_ram with pre-initialized firmware --- litex/soc/integration/soc_core.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index 6274216a2..512d105ca 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -64,7 +64,7 @@ class SoCCore(Module): cpu_type="lm32", cpu_reset_address=0x00000000, integrated_rom_size=0, integrated_sram_size=4096, - integrated_main_ram_size=0, + integrated_main_ram_size=0, integrated_main_ram_init=[], shadow_base=0x80000000, csr_data_width=8, csr_address_width=14, with_uart=True, uart_baudrate=115200, uart_stub=False, @@ -123,7 +123,7 @@ class SoCCore(Module): # Note: Main Ram can be used when no external SDRAM is available and use SDRAM mapping. if integrated_main_ram_size: - self.submodules.main_ram = wishbone.SRAM(integrated_main_ram_size) + self.submodules.main_ram = wishbone.SRAM(integrated_main_ram_size, init=integrated_main_ram_init) self.register_mem("main_ram", self.mem_map["main_ram"], self.main_ram.bus, integrated_main_ram_size) self.submodules.wishbone2csr = wishbone2csr.WB2CSR(