diff --git a/litex/gen/common.py b/litex/gen/common.py
index e4f108d9e..604cec853 100644
--- a/litex/gen/common.py
+++ b/litex/gen/common.py
@@ -19,6 +19,10 @@ def colorer(s, color="bright"):
     trailer = "\x1b[0m"
     return header + str(s) + trailer
 
+# Signals ------------------------------------------------------------------------------------------
+
+class Open(Signal) : pass
+
 # Bit/Bytes Reversing ------------------------------------------------------------------------------
 
 def reverse_bits(s):
diff --git a/litex/soc/cores/clock/efinix.py b/litex/soc/cores/clock/efinix.py
index 683c746ec..fc05120aa 100644
--- a/litex/soc/cores/clock/efinix.py
+++ b/litex/soc/cores/clock/efinix.py
@@ -8,11 +8,11 @@
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
+from litex.gen import *
+
 from litex.build.generic_platform import *
 from litex.soc.cores.clock.common import *
 
-class Open(Signal): pass
-
 # Efinix / TRIONPLL ----------------------------------------------------------------------------------
 
 class EFINIXPLL(Module):
diff --git a/litex/soc/cores/clock/gowin_gw1n.py b/litex/soc/cores/clock/gowin_gw1n.py
index c6a9ab462..1c563727c 100644
--- a/litex/soc/cores/clock/gowin_gw1n.py
+++ b/litex/soc/cores/clock/gowin_gw1n.py
@@ -7,9 +7,9 @@
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex.soc.cores.clock.common import *
+from litex.gen import *
 
-class Open(Signal): pass
+from litex.soc.cores.clock.common import *
 
 # GoWin / GW1NOSC ----------------------------------------------------------------------------------
 
diff --git a/litex/soc/cores/cpu/blackparrot/core.py b/litex/soc/cores/cpu/blackparrot/core.py
index 3e1b95e57..0f03ccdd7 100644
--- a/litex/soc/cores/cpu/blackparrot/core.py
+++ b/litex/soc/cores/cpu/blackparrot/core.py
@@ -31,16 +31,16 @@
 import os
 import sys
 from shutil import copyfile
+
 from migen import *
 
+from litex.gen import *
+
 from litex import get_data_mod
 from litex.soc.interconnect import axi
 from litex.soc.interconnect import wishbone
 from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV64
 
-class Open(Signal): pass
-
-
 # Variants -----------------------------------------------------------------------------------------
 
 CPU_VARIANTS = ["standard", "sim"]
diff --git a/litex/soc/cores/cpu/cortex_m1/core.py b/litex/soc/cores/cpu/cortex_m1/core.py
index 06afe0101..ee036e777 100644
--- a/litex/soc/cores/cpu/cortex_m1/core.py
+++ b/litex/soc/cores/cpu/cortex_m1/core.py
@@ -9,11 +9,11 @@ import os
 
 from migen import *
 
+from litex.gen import *
+
 from litex.soc.cores.cpu import CPU
 from litex.soc.interconnect import axi
 
-class Open(Signal): pass
-
 # Cortex-M1 ----------------------------------------------------------------------------------------
 
 class CortexM1(CPU):
diff --git a/litex/soc/cores/cpu/cortex_m3/core.py b/litex/soc/cores/cpu/cortex_m3/core.py
index e691920ce..d218c48d8 100644
--- a/litex/soc/cores/cpu/cortex_m3/core.py
+++ b/litex/soc/cores/cpu/cortex_m3/core.py
@@ -9,11 +9,11 @@ import os
 
 from migen import *
 
+from litex.gen import *
+
 from litex.soc.cores.cpu import CPU
 from litex.soc.interconnect import axi
 
-class Open(Signal): pass
-
 # Cortex-M3 ----------------------------------------------------------------------------------------
 
 class CortexM3(CPU):
diff --git a/litex/soc/cores/cpu/cva6/core.py b/litex/soc/cores/cpu/cva6/core.py
index d53b9b597..f046c17fd 100644
--- a/litex/soc/cores/cpu/cva6/core.py
+++ b/litex/soc/cores/cpu/cva6/core.py
@@ -10,13 +10,13 @@ import re
 
 from migen import *
 
+from litex.gen import *
+
 from litex import get_data_mod
 from litex.soc.interconnect import axi
 from litex.soc.interconnect import wishbone
 from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV64
 
-class Open(Signal): pass
-
 # Variants -----------------------------------------------------------------------------------------
 
 CPU_VARIANTS = ["standard", "full"]
diff --git a/litex/soc/cores/cpu/eos_s3/core.py b/litex/soc/cores/cpu/eos_s3/core.py
index 2640776d9..59deead2d 100644
--- a/litex/soc/cores/cpu/eos_s3/core.py
+++ b/litex/soc/cores/cpu/eos_s3/core.py
@@ -9,12 +9,12 @@ import os
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
+from litex.gen import *
+
 from litex.soc.interconnect import wishbone
 
 from litex.soc.cores.cpu import CPU
 
-class Open(Signal): pass
-
 # EOS-S3 -------------------------------------------------------------------------------------------
 
 class EOS_S3(CPU):
diff --git a/litex/soc/cores/cpu/ibex/core.py b/litex/soc/cores/cpu/ibex/core.py
index b84a6a751..495d2d46b 100644
--- a/litex/soc/cores/cpu/ibex/core.py
+++ b/litex/soc/cores/cpu/ibex/core.py
@@ -9,12 +9,12 @@ import os
 
 from migen import *
 
+from litex.gen import *
+
 from litex import get_data_mod
 from litex.soc.interconnect import wishbone
 from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV32
 
-class Open(Signal): pass
-
 # Variants -----------------------------------------------------------------------------------------
 
 CPU_VARIANTS = ["standard"]
diff --git a/litex/soc/cores/cpu/microwatt/core.py b/litex/soc/cores/cpu/microwatt/core.py
index e65c76e10..a2bc5d94f 100644
--- a/litex/soc/cores/cpu/microwatt/core.py
+++ b/litex/soc/cores/cpu/microwatt/core.py
@@ -10,6 +10,8 @@ import os
 
 from migen import *
 
+from litex.gen import *
+
 from litex import get_data_mod
 
 from litex.build.vhd2v_converter import *
@@ -19,8 +21,6 @@ from litex.soc.interconnect.csr import *
 from litex.gen.common import reverse_bytes
 from litex.soc.cores.cpu import CPU
 
-class Open(Signal): pass
-
 # Variants -----------------------------------------------------------------------------------------
 
 CPU_VARIANTS = ["standard", "standard+ghdl", "standard+irq", "standard+ghdl+irq"]
diff --git a/litex/soc/cores/cpu/naxriscv/core.py b/litex/soc/cores/cpu/naxriscv/core.py
index 8473692a6..3adc571a5 100755
--- a/litex/soc/cores/cpu/naxriscv/core.py
+++ b/litex/soc/cores/cpu/naxriscv/core.py
@@ -11,13 +11,13 @@ import subprocess
 
 from migen import *
 
+from litex.gen import *
+
 from litex import get_data_mod
 from litex.soc.interconnect import axi
 from litex.soc.interconnect.csr import *
 from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV32, CPU_GCC_TRIPLE_RISCV64
 
-class Open(Signal): pass
-
 # Variants -----------------------------------------------------------------------------------------
 
 CPU_VARIANTS = {
diff --git a/litex/soc/cores/cpu/neorv32/core.py b/litex/soc/cores/cpu/neorv32/core.py
index 7cd0ba0d0..b9d5c6656 100644
--- a/litex/soc/cores/cpu/neorv32/core.py
+++ b/litex/soc/cores/cpu/neorv32/core.py
@@ -8,6 +8,8 @@ import os
 
 from migen import *
 
+from litex.gen import *
+
 from litex.build.vhd2v_converter import *
 
 from litex.soc.interconnect import wishbone
@@ -65,8 +67,6 @@ class NEORV32(CPU):
 
         # # #
 
-        class Open(Signal) : pass
-
         # CPU LiteX Core Complex Wrapper
         self.specials += Instance("neorv32_litex_core_complex",
             # Clk/Rst.
diff --git a/litex/soc/cores/cpu/vexriscv_smp/core.py b/litex/soc/cores/cpu/vexriscv_smp/core.py
index 69ff2d034..25daa5b4c 100755
--- a/litex/soc/cores/cpu/vexriscv_smp/core.py
+++ b/litex/soc/cores/cpu/vexriscv_smp/core.py
@@ -6,21 +6,18 @@
 # SPDX-License-Identifier: BSD-2-Clause
 
 import os
-from os import path
 import subprocess
 
 from migen import *
 
+from litex.gen import *
+
 from litex import get_data_mod
 
 from litex.soc.interconnect import wishbone
 from litex.soc.interconnect.csr import *
 from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV32
 
-import os
-
-class Open(Signal): pass
-
 # VexRiscv SMP -------------------------------------------------------------------------------------
 
 class VexRiscvSMP(CPU):
@@ -363,7 +360,7 @@ class VexRiscvSMP(CPU):
     def add_sources(self, platform):
         vdir = get_data_mod("cpu", "vexriscv_smp").data_location
         print(f"VexRiscv cluster : {self.cluster_name}")
-        if not path.exists(os.path.join(vdir, self.cluster_name + ".v")):
+        if not os.path.exists(os.path.join(vdir, self.cluster_name + ".v")):
             self.generate_netlist()
 
 
diff --git a/litex/soc/cores/ram/xilinx_usp_hbm2.py b/litex/soc/cores/ram/xilinx_usp_hbm2.py
index 2778c91ba..b0ed356bd 100644
--- a/litex/soc/cores/ram/xilinx_usp_hbm2.py
+++ b/litex/soc/cores/ram/xilinx_usp_hbm2.py
@@ -9,6 +9,8 @@ import os
 
 from migen import *
 
+from litex.gen import *
+
 from litex.soc.cores.clock import *
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.builder import *
@@ -32,8 +34,6 @@ class USPHBM2(Module, AutoCSR):
 
         # # #
 
-        class Open(Signal): pass
-
         # Clocks -----------------------------------------------------------------------------------
         # Ref = 100 MHz (HBM: 900 (225-900) MHz), drives internal PLL (1 per stack).
         for i in range(2):
diff --git a/litex/soc/cores/video.py b/litex/soc/cores/video.py
index 93a0444dc..62b867c7b 100644
--- a/litex/soc/cores/video.py
+++ b/litex/soc/cores/video.py
@@ -12,6 +12,8 @@ import math
 from migen import *
 from migen.genlib.cdc import MultiReg
 
+from litex.gen import *
+
 from litex.soc.interconnect.csr import *
 from litex.soc.interconnect import stream
 from litex.soc.cores.code_tmds import TMDSEncoder
@@ -696,8 +698,6 @@ class VideoFrameBuffer(Module, AutoCSR):
 
 # Video PHYs ---------------------------------------------------------------------------------------
 
-class Open(Signal): pass
-
 # Generic (Very Generic PHY supporting VGA/DVI and variations).
 
 class VideoGenericPHY(Module):