From c2325983d5a244d2deb7929deeeac93d58c9ee21 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 8 Mar 2023 18:44:15 +0100 Subject: [PATCH] litex_sim/video: Cleanup and directly reuse VideoGenericPHY. --- litex/build/sim/core/modules/video/video.c | 15 ++--- litex/tools/litex_sim.py | 75 +++++++--------------- 2 files changed, 28 insertions(+), 62 deletions(-) diff --git a/litex/build/sim/core/modules/video/video.c b/litex/build/sim/core/modules/video/video.c index 9a3df407f..7549b5545 100644 --- a/litex/build/sim/core/modules/video/video.c +++ b/litex/build/sim/core/modules/video/video.c @@ -99,7 +99,6 @@ static int videosim_add_pads(void *sess, struct pad_list_s *plist) litex_sim_module_pads_get(pads, "hsync", (void**)&s->hsync); litex_sim_module_pads_get(pads, "vsync", (void**)&s->vsync); litex_sim_module_pads_get(pads, "de", (void**)&s->de); - litex_sim_module_pads_get(pads, "valid", (void**)&s->valid); litex_sim_module_pads_get(pads, "r", (void**)&s->r); litex_sim_module_pads_get(pads, "g", (void**)&s->g); litex_sim_module_pads_get(pads, "b", (void**)&s->b); @@ -154,16 +153,12 @@ static int videosim_tick(void *sess, uint64_t time_ps) { { if(s->pbuf) { - if(*s->valid) //mitigate underflow - { - *s->pbuf++ = *s->r; - *s->pbuf++ = *s->g; - *s->pbuf++ = *s->b; - s->pbuf++; - } + *s->pbuf++ = *s->r; + *s->pbuf++ = *s->g; + *s->pbuf++ = *s->b; + s->pbuf++; } - if(*s->valid) - s->x = s->x + 1; + s->x = s->x + 1; } else if(s->x != 0) { diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py index e96bc13d0..8fcb37bb2 100755 --- a/litex/tools/litex_sim.py +++ b/litex/tools/litex_sim.py @@ -43,6 +43,8 @@ from liteeth.core import LiteEthUDPIPCore from liteeth.frontend.etherbone import LiteEthEtherbone from liteeth.common import * +from litex.soc.cores.video import VideoGenericPHY + from litescope import LiteScopeAnalyzer # IOs ---------------------------------------------------------------------------------------------- @@ -127,15 +129,14 @@ _io = [ Subsignal("i", Pins(32)), ), - # Video + # Video (VGA). ("vga", 0, Subsignal("hsync", Pins(1)), Subsignal("vsync", Pins(1)), - Subsignal("de", Pins(1)), - Subsignal("valid", Pins(1)), - Subsignal("r", Pins(8)), - Subsignal("g", Pins(8)), - Subsignal("b", Pins(8)), + Subsignal("de", Pins(1)), + Subsignal("r", Pins(8)), + Subsignal("g", Pins(8)), + Subsignal("b", Pins(8)), ) ] @@ -145,36 +146,6 @@ class Platform(SimPlatform): def __init__(self): SimPlatform.__init__(self, "SIM", _io) -# Video -from litex.soc.cores.video import video_data_layout, video_timing_layout -class VideoPHYModel(Module, AutoCSR): - def __init__(self, pads, clock_domain="sys"): - self.sink = sink = stream.Endpoint(video_data_layout) - - # # # - - # Always ack Sink, no backpressure. - self.comb += sink.ready.eq(1) - - # Drive Clk. - if hasattr(pads, "clk"): - self.comb += pads.clk.eq(ClockSignal(clock_domain)) - - # Drive Controls. - self.comb += pads.valid.eq(1) #may be overriden with underflow from the framebuffer - self.comb += pads.de.eq(sink.de) - self.comb += pads.hsync.eq(sink.hsync) - self.comb += pads.vsync.eq(sink.vsync) - - # Drive Datas. - cbits = len(pads.r) - cshift = (8 - cbits) - for i in range(cbits): - self.comb += pads.r[i].eq(sink.r[cshift + i] & sink.de) - self.comb += pads.g[i].eq(sink.g[cshift + i] & sink.de) - self.comb += pads.b[i].eq(sink.b[cshift + i] & sink.de) - - # Simulation SoC ----------------------------------------------------------------------------------- class SimSoC(SoCCore): @@ -338,13 +309,13 @@ class SimSoC(SoCCore): # Video Framebuffer ------------------------------------------------------------------------ if with_video_framebuffer: video_pads = platform.request("vga") - self.submodules.videophy = VideoPHYModel(video_pads) + self.submodules.videophy = VideoGenericPHY(video_pads) self.add_video_framebuffer(phy=self.videophy, timings="640x480@60Hz", format="rgb888") self.videophy.comb += video_pads.valid.eq(~self.video_framebuffer.underflow) # Video Terminal --------------------------------------------------------------------------- if with_video_terminal: - self.submodules.videophy = VideoPHYModel(platform.request("vga")) + self.submodules.videophy = VideoGenericPHY(platform.request("vga")) self.add_video_terminal(phy=self.videophy, timings="640x480@60Hz") # Simulation debugging ---------------------------------------------------------------------- @@ -542,21 +513,21 @@ def main(): # SoC ------------------------------------------------------------------------------------------ soc = SimSoC( - with_sdram = args.with_sdram, - with_sdram_bist = args.with_sdram_bist, - with_ethernet = args.with_ethernet, - ethernet_phy_model = args.ethernet_phy_model, - with_etherbone = args.with_etherbone, - with_analyzer = args.with_analyzer, - with_i2c = args.with_i2c, - with_sdcard = args.with_sdcard, - with_spi_flash = args.with_spi_flash, - with_gpio = args.with_gpio, + with_sdram = args.with_sdram, + with_sdram_bist = args.with_sdram_bist, + with_ethernet = args.with_ethernet, + ethernet_phy_model = args.ethernet_phy_model, + with_etherbone = args.with_etherbone, + with_analyzer = args.with_analyzer, + with_i2c = args.with_i2c, + with_sdcard = args.with_sdcard, + with_spi_flash = args.with_spi_flash, + with_gpio = args.with_gpio, with_video_framebuffer = args.with_video_framebuffer, - with_video_terminal = args.with_video_terminal, - sim_debug = args.sim_debug, - trace_reset_on = int(float(args.trace_start)) > 0 or int(float(args.trace_end)) > 0, - spi_flash_init = None if args.spi_flash_init is None else get_mem_data(args.spi_flash_init, endianness="big"), + with_video_terminal = args.with_video_terminal, + sim_debug = args.sim_debug, + trace_reset_on = int(float(args.trace_start)) > 0 or int(float(args.trace_end)) > 0, + spi_flash_init = None if args.spi_flash_init is None else get_mem_data(args.spi_flash_init, endianness="big"), **soc_kwargs) if ram_boot_address is not None: if ram_boot_address == 0: