From c23a894014363bd76664f993fae2cc53d56c5596 Mon Sep 17 00:00:00 2001
From: Samuel Lindemer <samuel.lindemer@gmail.com>
Date: Mon, 14 Dec 2020 10:53:14 +0100
Subject: [PATCH] Allow selection of VexRiscv_Secure* from lxsim CLI

---
 litex/soc/cores/cpu/vexriscv/core.py | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py
index 6a1e33c85..f0d8a98a8 100644
--- a/litex/soc/cores/cpu/vexriscv/core.py
+++ b/litex/soc/cores/cpu/vexriscv/core.py
@@ -34,6 +34,8 @@ CPU_VARIANTS = {
     "linux":            "VexRiscv_Linux",
     "linux+debug":      "VexRiscv_LinuxDebug",
     "linux+no-dsp":     "VexRiscv_LinuxNoDspFmax",
+    "secure":           "VexRiscv_Secure",
+    "secure+debug":     "VexRiscv_SecureDebug",
 }
 
 
@@ -58,6 +60,8 @@ GCC_FLAGS = {
     "linux":            "-march=rv32ima    -mabi=ilp32",
     "linux+debug":      "-march=rv32ima    -mabi=ilp32",
     "linux+no-dsp":     "-march=rv32ima    -mabi=ilp32",
+    "secure":           "-march=rv32ima    -mabi=ilp32",
+    "secure+debug":     "-march=rv32ima    -mabi=ilp32",
 }