From c2714df198719ad77dbcfe00fd2bb6a9ae16c773 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Wed, 30 Aug 2023 11:25:27 +0200
Subject: [PATCH] build/efinix/common: Add initial
 EfinixDDROutput/EfinixDDRInput implementation.

Still need to figure out a few things:
- Clk is passed as a string for now.
- IOs exclusion still handled externally.
---
 litex/build/efinix/common.py | 63 ++++++++++++++++++++++++++++++++++++
 1 file changed, 63 insertions(+)

diff --git a/litex/build/efinix/common.py b/litex/build/efinix/common.py
index 1c307c8a5..5434db4ce 100644
--- a/litex/build/efinix/common.py
+++ b/litex/build/efinix/common.py
@@ -120,10 +120,73 @@ class EfinixSDRTristate(Module):
     def lower(dr):
         return EfinixSDRTristateImpl(dr.platform, dr.io, dr.o, dr.oe, dr.i, dr.clk)
 
+# Efinix DDROutput ---------------------------------------------------------------------------------
+
+class EfinixDDROutputImpl(Module):
+    def __init__(self, platform, i1, i2, o, clk):
+        io_name = platform.get_pin_name(o)
+        io_pad  = platform.get_pin_location(o)
+        io_prop = platform.get_pin_properties(o)
+        io_data_h  = platform.add_iface_io(io_name + "_HI")
+        io_data_l  = platform.add_iface_io(io_name + "_LO")
+        self.comb += io_data_h.eq(i1)
+        self.comb += io_data_l.eq(i2)
+        block = {
+            "type"              : "GPIO",
+            "mode"              : "OUTPUT",
+            "name"              : io_name,
+            "location"          : io_pad,
+            "properties"        : io_prop,
+            "size"              : 1,
+            "out_reg"           : "DDIO_RESYNC",
+            "out_clk_pin"       : clk, # FIXME.
+            "is_inclk_inverted" : False,
+            "drive_strength"    : 4 # FIXME: Get it from constraints.
+        }
+        platform.toolchain.ifacewriter.blocks.append(block)
+        # FIXME: Integrate IO exclusion.
+
+class EfinixDDROutput:
+    @staticmethod
+    def lower(dr):
+        return EfinixDDROutputImpl(dr.platform, dr.i1, dr.i2, dr.o, dr.clk)
+
+# Efinix DDRInput ----------------------------------------------------------------------------------
+
+class EfinixDDRInputImpl(Module):
+    def __init__(self, platform, i, o1, o2, clk):
+        io_name   = platform.get_pin_name(i)
+        io_pad    = platform.get_pin_location(i)
+        io_prop   = platform.get_pin_properties(i)
+        io_data_h = platform.add_iface_io(io_name + "_HI")
+        io_data_l = platform.add_iface_io(io_name + "_LO")
+        self.comb += o1.eq(io_data_h)
+        self.comb += o2.eq(io_data_l)
+        block = {
+            "type"              : "GPIO",
+            "mode"              : "INPUT",
+            "name"              : io_name,
+            "location"          : io_pad,
+            "properties"        : io_prop,
+            "size"              : 1,
+            "in_reg"            : "DDIO_RESYNC",
+            "in_clk_pin"        : clk, # FIXME.
+            "is_inclk_inverted" : False
+        }
+        platform.toolchain.ifacewriter.blocks.append(block)
+        # FIXME: Integrate IO exclusion.
+
+class EfinixDDRInput:
+    @staticmethod
+    def lower(dr):
+        return EfinixDDRInputImpl(dr.platform, dr.i, dr.o1, dr.o2, dr.clk)
+
 # Efinix Special Overrides -------------------------------------------------------------------------
 
 efinix_special_overrides = {
     AsyncResetSynchronizer : EfinixAsyncResetSynchronizer,
     Tristate               : EfinixTristate,
     SDRTristate            : EfinixSDRTristate,
+    DDROutput              : EfinixDDROutput,
+    DDRInput               : EfinixDDRInput,
 }