diff --git a/litex/soc/cores/clock/intel_common.py b/litex/soc/cores/clock/intel_common.py
index 6a0be5382..914d187d9 100644
--- a/litex/soc/cores/clock/intel_common.py
+++ b/litex/soc/cores/clock/intel_common.py
@@ -70,8 +70,8 @@ class IntelClocking(Module, AutoCSR):
                                 break
                             if valid:
                                 break
-                    if not valid:
-                        all_valid = False
+                        if not valid:
+                            all_valid = False
                 else:
                     all_valid = False
                 if all_valid: