From c44b906d9fccce956dcfce8dfa779d991130356c Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 27 Oct 2023 12:33:37 +0200
Subject: [PATCH] interconnect/stream: Revert Convert to Module, needs to be
 investigated.

---
 litex/soc/interconnect/stream.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/litex/soc/interconnect/stream.py b/litex/soc/interconnect/stream.py
index 797f1999f..c3759641e 100644
--- a/litex/soc/interconnect/stream.py
+++ b/litex/soc/interconnect/stream.py
@@ -470,7 +470,7 @@ def _get_converter_ratio(nbits_from, nbits_to):
     return converter_cls, ratio
 
 
-class Converter(LiteXModule):
+class Converter(Module): # FIXME: Switch to LiteXModule.
     def __init__(self, nbits_from, nbits_to,
         reverse                  = False,
         report_valid_token_count = False):