From c4e07e2a5bee2f5b05b10e00e15d70b38068b300 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 16 Jun 2022 17:47:13 +0200 Subject: [PATCH] integration/soc: Allow Bus Interconnect to use either InterconnectShared or Crossbar and add --bus-interconnect command line parameter. --- litex/soc/integration/soc.py | 27 +++++++++++++++++++++++---- litex/soc/integration/soc_core.py | 3 +++ litex/soc/interconnect/wishbone.py | 2 +- 3 files changed, 27 insertions(+), 5 deletions(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 5a795d430..4d5c1f31e 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -118,7 +118,15 @@ class SoCBusHandler(Module): supported_address_width = [32] # Creation ------------------------------------------------------------------------------------- - def __init__(self, name="SoCBusHandler", standard="wishbone", data_width=32, address_width=32, timeout=1e6, bursting=False, reserved_regions={}): + def __init__(self, name="SoCBusHandler", + standard = "wishbone", + data_width = 32, + address_width = 32, + timeout = 1e6, + bursting = False, + interconnect = "shared", + reserved_regions = {} + ): self.logger = logging.getLogger(name) self.logger.info("Creating Bus Handler...") @@ -151,6 +159,7 @@ class SoCBusHandler(Module): self.data_width = data_width self.address_width = address_width self.bursting = bursting + self.interconnect = interconnect self.masters = {} self.slaves = {} self.regions = {} @@ -743,6 +752,7 @@ class SoC(Module): bus_address_width = 32, bus_timeout = 1e6, bus_bursting = False, + bus_interconnect = "shared", bus_reserved_regions = {}, csr_data_width = 32, @@ -781,6 +791,7 @@ class SoC(Module): address_width = bus_address_width, timeout = bus_timeout, bursting = bus_bursting, + interconnect = bus_interconnect, reserved_regions = bus_reserved_regions, ) @@ -1065,6 +1076,10 @@ class SoC(Module): "wishbone": wishbone.InterconnectShared, "axi-lite": axi.AXILiteInterconnectShared, }[self.bus.standard] + interconnect_crossbar_cls = { + "wishbone": wishbone.Crossbar, + "axi-lite": axi.AXILiteCrossbar, + }[self.bus.standard] # SoC Reset -------------------------------------------------------------------------------- # Connect soc_rst to CRG's rst if present. @@ -1090,15 +1105,19 @@ class SoC(Module): self.submodules.bus_interconnect = interconnect_p2p_cls( master = next(iter(self.bus.masters.values())), slave = next(iter(self.bus.slaves.values()))) - # Otherwise, use InterconnectShared. + # Otherwise, use InterconnectShared/Crossbar. else: - self.submodules.bus_interconnect = interconnect_shared_cls( + interconnect_cls = { + "shared" : interconnect_shared_cls, + "crossbar": interconnect_crossbar_cls, + }[self.bus.interconnect] + self.submodules.bus_interconnect = interconnect_cls( masters = list(self.bus.masters.values()), slaves = [(self.bus.regions[n].decoder(self.bus), s) for n, s in self.bus.slaves.items()], register = True, timeout_cycles = self.bus.timeout) if hasattr(self, "ctrl") and self.bus.timeout is not None: - if hasattr(self.ctrl, "bus_error"): + if hasattr(self.ctrl, "bus_error") and hasattr(self.bus_interconnect, "timeout"): self.comb += self.ctrl.bus_error.eq(self.bus_interconnect.timeout.error) self.bus.logger.info("Interconnect: {} ({} <-> {}).".format( colorer(self.bus_interconnect.__class__.__name__), diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index e3c103175..d7208903f 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -65,6 +65,7 @@ class SoCCore(LiteXSoC): bus_address_width = 32, bus_timeout = 1e6, bus_bursting = False, + bus_interconnect = "shared", # CPU parameters cpu_type = "vexriscv", @@ -124,6 +125,7 @@ class SoCCore(LiteXSoC): bus_address_width = bus_address_width, bus_timeout = bus_timeout, bus_bursting = bus_bursting, + bus_interconnect = bus_interconnect, bus_reserved_regions = {}, csr_data_width = csr_data_width, @@ -304,6 +306,7 @@ def soc_core_args(parser): soc_group.add_argument("--bus-address-width", default=32, type=auto_int, help="Bus address-width.") soc_group.add_argument("--bus-timeout", default=int(1e6), type=float, help="Bus timeout in cycles.") soc_group.add_argument("--bus-bursting", action="store_true", help="Enable burst cycles on the bus if supported.") + soc_group.add_argument("--bus-interconnect", default="shared", help="Select bus interconnect: shared (default) or crossbar.") # CPU parameters soc_group.add_argument("--cpu-type", default="vexriscv", help="Select CPU: {}.".format(", ".join(iter(cpu.CPUS.keys())))) diff --git a/litex/soc/interconnect/wishbone.py b/litex/soc/interconnect/wishbone.py index bae02accd..9e3cf8f7f 100644 --- a/litex/soc/interconnect/wishbone.py +++ b/litex/soc/interconnect/wishbone.py @@ -223,7 +223,7 @@ class InterconnectShared(Module): class Crossbar(Module): - def __init__(self, masters, slaves, register=False): + def __init__(self, masters, slaves, register=False, timeout_cycles=1e6): matches, busses = zip(*slaves) access = [[Interface() for j in slaves] for i in masters] # decode each master into its access row