diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index cdd2d3cb4..d20e33680 100644
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -1638,6 +1638,7 @@ class LiteXSoC(SoC):
         ip_address              = "192.168.1.50",
         udp_port                = 1234,
         buffer_depth            = 16,
+        with_ip_broadcast       = True,
         with_timing_constraints = True):
         # Imports
         from liteeth.core import LiteEthUDPIPCore
@@ -1654,6 +1655,7 @@ class LiteXSoC(SoC):
             ip_address  = ip_address,
             clk_freq    = self.clk_freq,
             dw          = data_width,
+            with_ip_broadcast = with_ip_broadcast,
             with_sys_datapath = with_sys_datapath,
         )
         if not with_sys_datapath: