From c4fd6a7f2faffc883f8cd42ea318c841e6ec02e5 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 27 Feb 2020 13:00:35 +0100 Subject: [PATCH] targets/kc705: use DDRPHY_CMD_DELAY to center write leveling. --- litex/boards/targets/kc705.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py index 67cdf274c..874f39ab0 100755 --- a/litex/boards/targets/kc705.py +++ b/litex/boards/targets/kc705.py @@ -57,8 +57,10 @@ class BaseSoC(SoCSDRAM): self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"), memtype = "DDR3", nphases = 4, - sys_clk_freq = sys_clk_freq) + sys_clk_freq = sys_clk_freq, + cmd_latency = 1) self.add_csr("ddrphy") + self.add_constant("DDRPHY_CMD_DELAY", 13) sdram_module = MT8JTF12864(sys_clk_freq, "1:4") self.register_sdram(self.ddrphy, geom_settings = sdram_module.geom_settings,