From c51d22074f6815679942ed9968b7194be33d4f8a Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 22 Jul 2024 16:22:29 +0200 Subject: [PATCH] soc/integration/soc/add_uart: Allow directly passing uart_pads. Useful for test purpose when testing multiple UART peripherals without having to expose them on IOs. --- litex/soc/integration/soc.py | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 31d964032..6c286355f 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -1512,7 +1512,7 @@ class LiteXSoC(SoC): self.add_config(name, identifier) # Add UART ------------------------------------------------------------------------------------- - def add_uart(self, name="uart", uart_name="serial", baudrate=115200, fifo_depth=16): + def add_uart(self, name="uart", uart_name="serial", uart_pads=None, baudrate=115200, fifo_depth=16): # Imports. from litex.soc.cores.uart import UART, UARTCrossover @@ -1529,8 +1529,9 @@ class LiteXSoC(SoC): "usb_acm", "serial(x)", ] - uart_pads_name = "serial" if uart_name == "sim" else uart_name - uart_pads = self.platform.request(uart_pads_name, loose=True) + if uart_pads is None: + uart_pads_name = "serial" if uart_name == "sim" else uart_name + uart_pads = self.platform.request(uart_pads_name, loose=True) uart_phy = None uart = None uart_kwargs = {