diff --git a/misoclib/mem/sdram/module.py b/misoclib/mem/sdram/module.py
index d105adb8a..4572c001d 100644
--- a/misoclib/mem/sdram/module.py
+++ b/misoclib/mem/sdram/module.py
@@ -13,6 +13,7 @@
 #      configurations.
 #    - Modules can have different speedgrades, add support for it (and also add
 #      a check to verify clk_freq is in the supported range)
+#   Try to uniformize tREFI computations between modules
 
 from math import ceil