diff --git a/misoclib/mem/litesata/example_designs/targets/core.py b/misoclib/mem/litesata/example_designs/targets/core.py
index d841d4ecd..e15b259a8 100644
--- a/misoclib/mem/litesata/example_designs/targets/core.py
+++ b/misoclib/mem/litesata/example_designs/targets/core.py
@@ -17,7 +17,7 @@ class Core(Module):
         self.clk_freq = clk_freq
 
         # SATA PHY/Core/Frontend
-        self.submodules.sata_phy = LiteSATAPHY(platform.device, platform.request("sata"), "sata_gen2", clk_freq)
+        self.submodules.sata_phy = LiteSATAPHY(platform.device, platform.request("sys_clk"), platform.request("sata"), "sata_gen2", clk_freq)
         self.submodules.sata_core = LiteSATACore(self.sata_phy)
         self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_core)
 
diff --git a/misoclib/mem/litesata/test/Makefile b/misoclib/mem/litesata/test/Makefile
index 48228e975..ae0998fee 100644
--- a/misoclib/mem/litesata/test/Makefile
+++ b/misoclib/mem/litesata/test/Makefile
@@ -13,8 +13,7 @@ crc_tb:
 	$(CC) $(CFLAGS) $(INC) -o crc crc.c
 	$(CMD) crc_tb.py
 
-scrambler_tb:
-	$(CC) $(CFLAGS) $(INC) -o scrambler scrambler.c
+scrambler_tb: scrambler
 	$(CMD) scrambler_tb.py
 
 cont_tb:
@@ -26,7 +25,7 @@ link_tb:
 command_tb:
 	$(CMD) command_tb.py
 
-bist_tb:
+bist_tb: scrambler
 	$(CMD) bist_tb.py
 
 striping_tb:
@@ -35,5 +34,8 @@ striping_tb:
 mirroring_tb:
 	$(CMD) mirroring_tb.py
 
+scrambler: scrambler.c
+	$(CC) $(CFLAGS) $(INC) -o $@ $<
+
 clean:
-	rm crc scrambler *.vcd
+	rm -f crc scrambler *.vcd