From c6f6d7b491f0c8227e28e171eea84d72bcb744e6 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 30 Jun 2017 19:41:14 +0200 Subject: [PATCH] soc/interconnect/wishbonebridge: reset_less optimizations --- litex/soc/interconnect/wishbonebridge.py | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/litex/soc/interconnect/wishbonebridge.py b/litex/soc/interconnect/wishbonebridge.py index b3be5bd88..b9f9d1095 100644 --- a/litex/soc/interconnect/wishbonebridge.py +++ b/litex/soc/interconnect/wishbonebridge.py @@ -19,7 +19,7 @@ class WishboneStreamingBridge(Module): # # # - byte_counter = Signal(3) + byte_counter = Signal(3, reset_less=True) byte_counter_reset = Signal() byte_counter_ce = Signal() self.sync += \ @@ -29,7 +29,7 @@ class WishboneStreamingBridge(Module): byte_counter.eq(byte_counter + 1) ) - word_counter = Signal(3) + word_counter = Signal(3, reset_less=True) word_counter_reset = Signal() word_counter_ce = Signal() self.sync += \ @@ -39,16 +39,16 @@ class WishboneStreamingBridge(Module): word_counter.eq(word_counter + 1) ) - cmd = Signal(8) + cmd = Signal(8, reset_less=True) cmd_ce = Signal() - length = Signal(8) + length = Signal(8, reset_less=True) length_ce = Signal() - address = Signal(32) + address = Signal(32, reset_less=True) address_ce = Signal() - data = Signal(32) + data = Signal(32, reset_less=True) rx_data_ce = Signal() tx_data_ce = Signal()