diff --git a/litex/soc/cores/cpu/vexriscv_smp/core.py b/litex/soc/cores/cpu/vexriscv_smp/core.py
index 2fe30c20c..3835ac253 100755
--- a/litex/soc/cores/cpu/vexriscv_smp/core.py
+++ b/litex/soc/cores/cpu/vexriscv_smp/core.py
@@ -169,7 +169,6 @@ class VexRiscvSMP(CPU):
     def gcc_flags(self):
         flags =  f" -march={VexRiscvSMP.get_arch()} -mabi={VexRiscvSMP.get_abi()}"
         flags += f" -D__vexriscv_smp__"
-        #flags += f" -DUART_POLLING"
         return flags
 
     # Reserved Interrupts.
diff --git a/litex/soc/cores/cpu/vexriscv_smp/irq.h b/litex/soc/cores/cpu/vexriscv_smp/irq.h
index c50d44679..4c8461447 100644
--- a/litex/soc/cores/cpu/vexriscv_smp/irq.h
+++ b/litex/soc/cores/cpu/vexriscv_smp/irq.h
@@ -18,7 +18,7 @@ extern "C" {
 #define PLIC_THRSHLD 0xf0e00000L // Per-pin priority must be >= this to trigger
 #define PLIC_CLAIM   0xf0e00004L // Claim & completion register address
 
-#define PLIC_EXT_IRQ_BASE 0 // CHECKME/FIXME.
+#define PLIC_EXT_IRQ_BASE 0
 
 static inline unsigned int irq_getie(void)
 {