From c79e1ef95f0e0c7514deffac1d6e722d278ff18e Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 14 May 2024 14:43:57 +0200 Subject: [PATCH] cores/cpu/vexriscv_smp: Remove FIXME/CHECKME now that working and remove UART_POLLING flag. --- litex/soc/cores/cpu/vexriscv_smp/core.py | 1 - litex/soc/cores/cpu/vexriscv_smp/irq.h | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/litex/soc/cores/cpu/vexriscv_smp/core.py b/litex/soc/cores/cpu/vexriscv_smp/core.py index 2fe30c20c..3835ac253 100755 --- a/litex/soc/cores/cpu/vexriscv_smp/core.py +++ b/litex/soc/cores/cpu/vexriscv_smp/core.py @@ -169,7 +169,6 @@ class VexRiscvSMP(CPU): def gcc_flags(self): flags = f" -march={VexRiscvSMP.get_arch()} -mabi={VexRiscvSMP.get_abi()}" flags += f" -D__vexriscv_smp__" - #flags += f" -DUART_POLLING" return flags # Reserved Interrupts. diff --git a/litex/soc/cores/cpu/vexriscv_smp/irq.h b/litex/soc/cores/cpu/vexriscv_smp/irq.h index c50d44679..4c8461447 100644 --- a/litex/soc/cores/cpu/vexriscv_smp/irq.h +++ b/litex/soc/cores/cpu/vexriscv_smp/irq.h @@ -18,7 +18,7 @@ extern "C" { #define PLIC_THRSHLD 0xf0e00000L // Per-pin priority must be >= this to trigger #define PLIC_CLAIM 0xf0e00004L // Claim & completion register address -#define PLIC_EXT_IRQ_BASE 0 // CHECKME/FIXME. +#define PLIC_EXT_IRQ_BASE 0 static inline unsigned int irq_getie(void) {