From c80d5723c957f7b9f169c9b121891102eb231937 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 30 Jul 2021 12:32:57 +0200 Subject: [PATCH] soc/add_spi_flash: Reduce default_divisor. --- litex/soc/integration/soc.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index ac9058991..00ff92038 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -1497,7 +1497,7 @@ class LiteXSoC(SoC): self.check_if_exists(name + "_phy") self.check_if_exists(name + "_mmap") spiflash_pads = self.platform.request(name if mode == "1x" else name + mode) - spiflash_phy = LiteSPIPHY(spiflash_pads, module, default_divisor=max(int(self.sys_clk_freq/clk_freq), 2)) + spiflash_phy = LiteSPIPHY(spiflash_pads, module, default_divisor=int(self.sys_clk_freq/clk_freq)) spiflash_core = LiteSPI(spiflash_phy, clk_freq=clk_freq, mmap_endianness=self.cpu.endianness, **kwargs) setattr(self.submodules, name + "_phy", spiflash_phy) setattr(self.submodules, name + "_core", spiflash_core)