From c8343879651b2f2126f569c86818189cca676e89 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 10 Jan 2023 11:09:45 +0100 Subject: [PATCH] soc/cores/hyperbus: Expose burst_timer to ease debug. --- litex/soc/cores/hyperbus.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/cores/hyperbus.py b/litex/soc/cores/hyperbus.py index 584349caa..594c3791e 100644 --- a/litex/soc/cores/hyperbus.py +++ b/litex/soc/cores/hyperbus.py @@ -65,7 +65,7 @@ class HyperRAM(Module): # Burst Timer ------------------------------------------------------------------------------ sys_clk_freq = 10e6 if sys_clk_freq is None else sys_clk_freq burst_timer = WaitTimer(int(sys_clk_freq*self.tCSM)) - self.submodules += burst_timer + self.submodules.burst_timer = burst_timer # Clock Generation (sys_clk/4) ------------------------------------------------------------- self.sync += clk_phase.eq(clk_phase + 1)