From c8a9f205e0cd44e7eac1f3d2ccc57e955a0c3b2d Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Tue, 14 Nov 2023 21:06:25 +0100 Subject: [PATCH] soc/cores/clock/efinix: allowing to specify LVDS input refclk name (Trion) --- litex/soc/cores/clock/efinix.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/litex/soc/cores/clock/efinix.py b/litex/soc/cores/clock/efinix.py index fae23d7d4..9dd61647d 100644 --- a/litex/soc/cores/clock/efinix.py +++ b/litex/soc/cores/clock/efinix.py @@ -55,7 +55,7 @@ class EFINIXPLL(LiteXModule): self.comb += self.platform.add_iface_io(self.name + "_rstn").eq(~self.reset) self.comb += self.locked.eq(self.platform.add_iface_io(self.name + "_locked")) - def register_clkin(self, clkin, freq, name="", lvds_input=False): + def register_clkin(self, clkin, freq, name="", refclk_name="", lvds_input=False): block = self.platform.toolchain.ifacewriter.get_block(self.name) block["input_clock_name"] = self.platform.get_pin_name(clkin) @@ -81,6 +81,7 @@ class EFINIXPLL(LiteXModule): block["input_clock"] = "EXTERNAL" if not lvds_input else "LVDS_RX" block["input_clock_pad"] = pin_name + block["input_refclk_name"] = refclk_name block["resource"] = pll_res block["clock_no"] = clock_no self.logger.info("Clock source: {}, using EXT_CLK{}".format(block["input_clock"], clock_no))