From c8fcaaea2df5b6cd11cec4b5fb86eccf3d424bce Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 30 Nov 2020 10:17:03 +0100 Subject: [PATCH] integration/soc: use self.irq.enabled instead of hasattr(self.cpu, "interrupt"). --- litex/soc/integration/soc.py | 6 +++--- litex/tools/litex_sim.py | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 3dd9b5d45..3d8d94613 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -905,7 +905,7 @@ class SoC(Module): self.check_if_exists(name) setattr(self.submodules, name, Timer()) self.csr.add(name, use_loc_if_exists=True) - if hasattr(self.cpu, "interrupt"): + if self.irq.enabled: self.irq.add(name, use_loc_if_exists=True) # SoC finalization ----------------------------------------------------------------------------- @@ -1141,7 +1141,7 @@ class LiteXSoC(SoC): self.csr.add("uart_phy", use_loc_if_exists=True) self.csr.add("uart", use_loc_if_exists=True) - if hasattr(self.cpu, "interrupt"): + if self.irq.enabled: self.irq.add("uart", use_loc_if_exists=True) else: self.add_constant("UART_POLLING") @@ -1333,7 +1333,7 @@ class LiteXSoC(SoC): ethmac_region = SoCRegion(origin=self.mem_map.get(name, None), size=0x2000, cached=False) self.bus.add_slave(name=name, slave=ethmac.bus, region=ethmac_region) self.csr.add(name, use_loc_if_exists=True) - if hasattr(self.cpu, "interrupt"): + if self.irq.enabled: self.irq.add(name, use_loc_if_exists=True) # Timing constraints if hasattr(phy, "crg"): diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py index 1154e41d5..ccb30e9bb 100755 --- a/litex/tools/litex_sim.py +++ b/litex/tools/litex_sim.py @@ -236,7 +236,7 @@ class SimSoC(SoCCore): self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000) self.add_csr("ethmac") - if hasattr(self.cpu, "interrupt"): + if self.irq.enabled: self.irq.add("ethmac", use_loc_if_exists=True) # HW ethernet self.submodules.arp = LiteEthARP(self.ethmac, etherbone_mac_address, etherbone_ip_address, sys_clk_freq, dw=8) @@ -262,7 +262,7 @@ class SimSoC(SoCCore): self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000) self.add_csr("ethmac") - if hasattr(self.cpu, "interrupt"): + if self.irq.enabled: self.irq.add("ethmac", use_loc_if_exists=True) # Etherbone --------------------------------------------------------------------------------