diff --git a/litex/boards/platforms/avalanche.py b/litex/boards/platforms/avalanche.py
index cd71f7917..62ec2a346 100644
--- a/litex/boards/platforms/avalanche.py
+++ b/litex/boards/platforms/avalanche.py
@@ -40,27 +40,28 @@ _io = [
         IOStandard("LVCMOS25"),
     ),
 
-    # FIXME: add IO constraints
     ("ddram", 0,
         Subsignal("a", Pins(
             "U5 U4 V4 W3 V5 W4 Y3 AA3",
-            "Y4 Y5 AA2 AB2 V6 W6 AB3")),
-        Subsignal("ba", Pins("V7 Y6 U7")),
-        Subsignal("ras_n", Pins("AA6")),
-        Subsignal("cas_n", Pins("AA5")),
-        Subsignal("we_n", Pins("AB5")),
-        Subsignal("cs_n", Pins("W7")),
-        Subsignal("dm", Pins("Y9 R15")),
+            "Y4 Y5 AA2 AB2 V6 W6 AB3"),
+            IOStandard("SSTL15II")),
+        Subsignal("ba", Pins("V7 Y6 U7"), IOStandard("SSTL15II")),
+        Subsignal("ras_n", Pins("AA6"), IOStandard("SSTL15II")),
+        Subsignal("cas_n", Pins("AA5"), IOStandard("SSTL15II")),
+        Subsignal("we_n", Pins("AB5"), IOStandard("SSTL15II")),
+        Subsignal("cs_n", Pins("W7"), IOStandard("SSTL15II")),
+        Subsignal("dm", Pins("Y9 R15"), IOStandard("SSTL15II")),
         Subsignal("dq", Pins(
             "T7 T8 U8 U9 R10 V9 V10 W9",
-            "V14 U14 R12 T11 U15 T13 U13 T15")),
-        Subsignal("dqs_p", Pins("T10 R13")),
-        Subsignal("dqs_n", Pins("U10 T12")),
-        Subsignal("clk_p", Pins("V2")),
-        Subsignal("clk_n", Pins("W2")),
-        Subsignal("cke", Pins("W8")),
-        Subsignal("odt", Pins("AA7")),
-        Subsignal("reset_n", Pins("AB7")),
+            "V14 U14 R12 T11 U15 T13 U13 T15"),
+            IOStandard("SSTL15II")),
+        Subsignal("dqs_p", Pins("T10 R13"), IOStandard("SSTL15II")),
+        Subsignal("dqs_n", Pins("U10 T12"), IOStandard("SSTL15II")),
+        Subsignal("clk_p", Pins("V2"), IOStandard("SSTL15II")),
+        Subsignal("clk_n", Pins("W2"), IOStandard("SSTL15II")),
+        Subsignal("cke", Pins("W8"), IOStandard("SSTL15II")),
+        Subsignal("odt", Pins("AA7"), IOStandard("SSTL15II")),
+        Subsignal("reset_n", Pins("AB7"), IOStandard("SSTL15II")),
     ),
 
     ("eth_clocks", 0,