From c97fabb2856714170a9c28bbd1ac61d2e361ed37 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 10 Mar 2020 16:48:07 +0100 Subject: [PATCH] targets/kcu105: simplify CRG using USIDELAYCTRL. --- litex/boards/targets/kcu105.py | 36 +++++----------------------------- 1 file changed, 5 insertions(+), 31 deletions(-) diff --git a/litex/boards/targets/kcu105.py b/litex/boards/targets/kcu105.py index 75e6805ab..0b23fd703 100755 --- a/litex/boards/targets/kcu105.py +++ b/litex/boards/targets/kcu105.py @@ -26,7 +26,6 @@ class _CRG(Module): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) self.clock_domains.cd_clk200 = ClockDomain() - self.clock_domains.cd_ic = ClockDomain() # # # @@ -46,33 +45,7 @@ class _CRG(Module): AsyncResetSynchronizer(self.cd_clk200, ~pll.locked), ] - ic_reset_counter = Signal(max=64, reset=63) - ic_reset = Signal(reset=1) - self.sync.clk200 += \ - If(ic_reset_counter != 0, - ic_reset_counter.eq(ic_reset_counter - 1) - ).Else( - ic_reset.eq(0) - ) - ic_rdy = Signal() - ic_rdy_counter = Signal(max=64, reset=63) - self.cd_sys.rst.reset = 1 - self.comb += self.cd_ic.clk.eq(self.cd_sys.clk) - self.sync.ic += [ - If(ic_rdy, - If(ic_rdy_counter != 0, - ic_rdy_counter.eq(ic_rdy_counter - 1) - ).Else( - self.cd_sys.rst.eq(0) - ) - ) - ] - self.specials += [ - Instance("IDELAYCTRL", p_SIM_DEVICE="ULTRASCALE", - i_REFCLK=ClockSignal("clk200"), i_RST=ic_reset, - o_RDY=ic_rdy), - AsyncResetSynchronizer(self.cd_ic, ic_reset) - ] + self.submodules.idelayctrl = USIDELAYCTRL(cd_ref=self.cd_clk200, cd_sys=self.cd_sys) # BaseSoC ------------------------------------------------------------------------------------------ @@ -89,11 +62,12 @@ class BaseSoC(SoCSDRAM): # DDR4 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = usddrphy.USDDRPHY(platform.request("ddram"), - memtype = "DDR4", - sys_clk_freq = sys_clk_freq) + memtype = "DDR4", + sys_clk_freq = sys_clk_freq, + iodelay_clk_freq = 200e6, + cmd_latency = 0) self.add_csr("ddrphy") self.add_constant("USDDRPHY", None) - self.add_constant("USDDRPHY_DEBUG", None) sdram_module = EDY4016A(sys_clk_freq, "1:4") self.register_sdram(self.ddrphy, geom_settings = sdram_module.geom_settings,