From c99c96bc68911fdf0661841f22acbd507d12117e Mon Sep 17 00:00:00 2001 From: rprinz08 Date: Tue, 22 Dec 2020 21:13:10 +0100 Subject: [PATCH] Enable etherbone usage on multiple ethernet interfaces --- litex/soc/integration/soc.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 4d7d3b1cb..646a29749 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -1362,7 +1362,7 @@ class LiteXSoC(SoC): eth_tx_clk) # Add Etherbone -------------------------------------------------------------------------------- - def add_etherbone(self, name="etherbone", phy=None, + def add_etherbone(self, name="etherbone", phy=None, phy_cd="eth", mac_address = 0x10e2d5000000, ip_address = "192.168.1.50", udp_port = 1234, @@ -1377,7 +1377,9 @@ class LiteXSoC(SoC): mac_address = mac_address, ip_address = ip_address, clk_freq = self.clk_freq) - ethcore = ClockDomainsRenamer("eth_tx")(ethcore) + ethcore = ClockDomainsRenamer({ + "eth_tx": phy_cd + "_tx", + "eth_rx": phy_cd + "_rx"})(ethcore) self.submodules.ethcore = ethcore # Clock domain renaming