From c9c11e7aa837a266446cdaab5f869b7cfe1d2fac Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 3 Apr 2015 12:45:32 +0200 Subject: [PATCH] soc: add memory.name_override to name when adding csrbankarray.srams to csr_regions --- misoclib/soc/__init__.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/misoclib/soc/__init__.py b/misoclib/soc/__init__.py index 441ad5e43..f900dac91 100644 --- a/misoclib/soc/__init__.py +++ b/misoclib/soc/__init__.py @@ -179,7 +179,7 @@ class SoC(Module): for name, csrs, mapaddr, rmap in self.csrbankarray.banks: self.add_csr_region(name, self.mem_map["csr"]+0x80000000+0x800*mapaddr, self.csr_data_width, csrs) for name, memory, mapaddr, mmap in self.csrbankarray.srams: - self.add_csr_region(name, self.mem_map["csr"]+0x80000000+0x800*mapaddr, self.csr_data_width, memory) + self.add_csr_region(name + "_" + memory.name_override, self.mem_map["csr"]+0x80000000+0x800*mapaddr, self.csr_data_width, memory) # Interrupts if hasattr(self.cpu_or_bridge, "interrupt"):