From c9ed38dec815d165404a386db35e420fb8ecabac Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Thu, 26 Feb 2015 20:19:39 -0700 Subject: [PATCH] gensoc: missing self. --- misoclib/gensoc/__init__.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/misoclib/gensoc/__init__.py b/misoclib/gensoc/__init__.py index ae8805297..46068cccc 100644 --- a/misoclib/gensoc/__init__.py +++ b/misoclib/gensoc/__init__.py @@ -193,7 +193,7 @@ class SDRAMSoC(GenSoC): self.add_wb_slave(mem_decoder(self.mem_map["sdram"]), sdramcon.bus) elif (sdram_width < 32): self.submodules.dc = wishbone.DownConverter(32, sdram_width) - self.submodules.intercon = wishbone.InterconnectPointToPoint(dc.wishbone_o, sdramcon.bus) + self.submodules.intercon = wishbone.InterconnectPointToPoint(self.dc.wishbone_o, sdramcon.bus) self.add_wb_slave(mem_decoder(self.mem_map["sdram"]), self.dc.wishbone_i) else: raise NotImplementedError("Unsupported SDRAM width of {} > 32".format(sdram_width))