From ca04858b391eab791a1dfd818a2cb8d1d1dd9864 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 2 Apr 2024 10:16:43 +0200 Subject: [PATCH] integration/builder: Switch to SoC.init_rom directly and remove initialize_rom that is no longer used. --- litex/soc/integration/builder.py | 2 +- litex/soc/integration/soc_core.py | 3 --- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/litex/soc/integration/builder.py b/litex/soc/integration/builder.py index d11e94bbb..fbfe7673a 100644 --- a/litex/soc/integration/builder.py +++ b/litex/soc/integration/builder.py @@ -331,7 +331,7 @@ class Builder: ) # Initialize SoC with with BIOS data. - self.soc.initialize_rom(bios_data) + self.soc.init_rom(name="rom", contents=bios_data) def build(self, **kwargs): # Pass Output Directory to Platform. diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index 38dc1f926..7e89c9c0d 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -271,9 +271,6 @@ class SoCCore(LiteXSoC): def add_csr(self, csr_name, csr_id=None, use_loc_if_exists=False): self.csr.add(csr_name, csr_id, use_loc_if_exists=use_loc_if_exists) - def initialize_rom(self, data): - self.init_rom(name="rom", contents=data) - def add_memory_region(self, name, origin, length, type="cached"): self.bus.add_region(name, SoCRegion(origin=origin, size=length, cached="cached" in type,