From ca6378a2078794d0b6ddcc9bbbbde82f25d82783 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Wed, 20 Apr 2022 15:13:04 +0200 Subject: [PATCH] cpu/NaxRiscv: Improve place and route timings robustness --- litex/soc/cores/cpu/naxriscv/core.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litex/soc/cores/cpu/naxriscv/core.py b/litex/soc/cores/cpu/naxriscv/core.py index 15328ee70..4535ae6fe 100644 --- a/litex/soc/cores/cpu/naxriscv/core.py +++ b/litex/soc/cores/cpu/naxriscv/core.py @@ -229,8 +229,8 @@ class NaxRiscv(CPU): ndir = os.path.join(vdir, "ext", "NaxRiscv") sdir = os.path.join(vdir, "ext", "SpinalHDL") - NaxRiscv.git_setup("NaxRiscv", ndir, "https://github.com/SpinalHDL/NaxRiscv.git" , "dev" , "d97112e1") - NaxRiscv.git_setup("SpinalHDL", sdir, "https://github.com/SpinalHDL/SpinalHDL.git", "dev" , "e1e5961d") + NaxRiscv.git_setup("NaxRiscv", ndir, "https://github.com/SpinalHDL/NaxRiscv.git" , "dev" , "8b4449f9") + NaxRiscv.git_setup("SpinalHDL", sdir, "https://github.com/SpinalHDL/SpinalHDL.git", "dev" , "4c024e93") gen_args = [] gen_args.append(f"--netlist-name={NaxRiscv.netlist_name}")