From ca6b9aa6e3b14929fe84ea9adbe59b45947b63d6 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 1 Dec 2015 10:20:16 +0100 Subject: [PATCH] boards/targets: add default rom/ram configuration for arty --- litex/boards/targets/arty.py | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py index eb07d1ae5..35b67026b 100644 --- a/litex/boards/targets/arty.py +++ b/litex/boards/targets/arty.py @@ -72,7 +72,11 @@ class _CRG(Module): class BaseSoC(SoCCore): def __init__(self, **kwargs): platform = arty.Platform() - SoCCore.__init__(self, platform, clk_freq=100*1000000, **kwargs) + SoCCore.__init__(self, platform, clk_freq=100*1000000, + integrated_rom_size=0x8000, + integrated_sram_size=0x8000, + integrated_main_ram_size=0x10000, + **kwargs) self.submodules.crg = _CRG(platform)