From ca78f799e1e07c99373dac14e4bb292ce9f71a83 Mon Sep 17 00:00:00 2001 From: Rafal Kolucki Date: Tue, 5 Apr 2022 14:15:26 +0200 Subject: [PATCH] soc/integration/soc_core: Add SRAM/ROM burst cycles support switch --- litex/soc/integration/soc.py | 10 +++++----- litex/soc/integration/soc_core.py | 20 ++++++++++++++------ 2 files changed, 19 insertions(+), 11 deletions(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 1fe83b03c..d76a75356 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -837,7 +837,7 @@ class SoC(Module): colorer("added", color="green"))) setattr(self.submodules, name, SoCController(**kwargs)) - def add_ram(self, name, origin, size, contents=[], mode="rw"): + def add_ram(self, name, origin, size, contents=[], mode="rw", burst=False): ram_cls = { "wishbone": wishbone.SRAM, "axi-lite": axi.AXILiteSRAM, @@ -847,7 +847,7 @@ class SoC(Module): "axi-lite": axi.AXILiteInterface, }[self.bus.standard] ram_bus = interface_cls(data_width=self.bus.data_width) - ram = ram_cls(size, bus=ram_bus, init=contents, read_only=(mode == "r")) + ram = ram_cls(size, bus=ram_bus, init=contents, read_only=(mode == "r"), burst=burst) self.bus.add_slave(name, ram.bus, SoCRegion(origin=origin, size=size, mode=mode)) self.check_if_exists(name) self.logger.info("RAM {} {} {}.".format( @@ -858,8 +858,8 @@ class SoC(Module): if contents != []: self.add_config(f"{name}_INIT", 1) - def add_rom(self, name, origin, size, contents=[], mode="r"): - self.add_ram(name, origin, size, contents, mode=mode) + def add_rom(self, name, origin, size, contents=[], mode="r", burst=False): + self.add_ram(name, origin, size, contents, mode=mode, burst=burst) def init_rom(self, name, contents=[], auto_size=True): self.logger.info("Initializing ROM {} with contents (Size: {}).".format( @@ -1971,4 +1971,4 @@ class LiteXSoCArgumentParser(argparse.ArgumentParser): if cpu_cls is not None and hasattr(cpu_cls, "args_read"): cpu_cls.args_read(args) - return args \ No newline at end of file + return args diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index cc707ae6c..bce2d3be3 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -78,14 +78,17 @@ class SoCCore(LiteXSoC): integrated_rom_size = 0, integrated_rom_mode = "r", integrated_rom_init = [], + integrated_rom_burst = False, # SRAM parameters integrated_sram_size = 0x2000, integrated_sram_init = [], + integrated_sram_burst = False, # MAIN_RAM parameters - integrated_main_ram_size = 0, - integrated_main_ram_init = [], + integrated_main_ram_size = 0, + integrated_main_ram_init = [], + integrated_main_ram_burst = False, # CSR parameters csr_data_width = 32, @@ -198,7 +201,8 @@ class SoCCore(LiteXSoC): origin = self.cpu.reset_address, size = integrated_rom_size, contents = integrated_rom_init, - mode = integrated_rom_mode + mode = integrated_rom_mode, + burst = integrated_rom_burst ) # Add integrated SRAM @@ -206,6 +210,7 @@ class SoCCore(LiteXSoC): self.add_ram("sram", origin = self.mem_map["sram"], size = integrated_sram_size, + burst = integrated_sram_burst ) # Add integrated MAIN_RAM (only useful when no external SRAM/SDRAM is available) @@ -214,6 +219,7 @@ class SoCCore(LiteXSoC): origin = self.mem_map["main_ram"], size = integrated_main_ram_size, contents = integrated_main_ram_init, + burst = integrated_main_ram_burst, ) # Add Identifier @@ -312,11 +318,13 @@ def soc_core_args(parser): soc_group.add_argument("--no-ctrl", action="store_true", help="Disable Controller.") # ROM parameters - soc_group.add_argument("--integrated-rom-size", default=0x20000, type=auto_int, help="Size/Enable the integrated (BIOS) ROM (Automatically resized to BIOS size when smaller).") - soc_group.add_argument("--integrated-rom-init", default=None, type=str, help="Integrated ROM binary initialization file (override the BIOS when specified).") + soc_group.add_argument("--integrated-rom-size", default=0x20000, type=auto_int, help="Size/Enable the integrated (BIOS) ROM (Automatically resized to BIOS size when smaller).") + soc_group.add_argument("--integrated-rom-init", default=None, type=str, help="Integrated ROM binary initialization file (override the BIOS when specified).") + soc_group.add_argument("--integrated-rom-burst", default=False, action="store_true", help="Enable burst cycles support in integrated ROM (works only for Wishbone interconnect).") # SRAM parameters - soc_group.add_argument("--integrated-sram-size", default=0x2000, type=auto_int, help="Size/Enable the integrated SRAM.") + soc_group.add_argument("--integrated-sram-size", default=0x2000, type=auto_int, help="Size/Enable the integrated SRAM.") + soc_group.add_argument("--integrated-sram-burst", default=False, action="store_true", help="Enable burst cycles support in integrated ROM (works only for Wishbone interconnect).") # MAIN_RAM parameters soc_group.add_argument("--integrated-main-ram-size", default=None, type=auto_int, help="size/enable the integrated main RAM.")