From 219bb7f294c14dde5072ac3282cc33943931a64c Mon Sep 17 00:00:00 2001 From: bunnie Date: Wed, 1 Jan 2020 18:49:00 +0800 Subject: [PATCH] add the possibility for a "precise" clock solution If clocks and multipliers are planned well, we can have a zero-error solution for clocks. Suggest to change < to <= in margin comparison loop, so that a "perfect" solution is allowed to converge. --- litex/soc/cores/clock.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/cores/clock.py b/litex/soc/cores/clock.py index 5d3ce6ec4..03b7e426c 100644 --- a/litex/soc/cores/clock.py +++ b/litex/soc/cores/clock.py @@ -74,7 +74,7 @@ class XilinxClocking(Module, AutoCSR): valid = False for d in range(*self.clkout_divide_range): clk_freq = vco_freq/d - if abs(clk_freq - f) < f*m: + if abs(clk_freq - f) <= f*m: config["clkout{}_freq".format(n)] = clk_freq config["clkout{}_divide".format(n)] = d config["clkout{}_phase".format(n)] = p