From cb008a061cea67599ce3710bf5aaa0eeb9706015 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sun, 5 May 2013 12:58:24 +0200 Subject: [PATCH] dvisampler/chansync: fix FIFO width --- milkymist/dvisampler/chansync.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/milkymist/dvisampler/chansync.py b/milkymist/dvisampler/chansync.py index 5f53de18b..95dd6802a 100644 --- a/milkymist/dvisampler/chansync.py +++ b/milkymist/dvisampler/chansync.py @@ -2,7 +2,7 @@ from migen.fhdl.structure import * from migen.fhdl.module import Module from migen.genlib.cdc import MultiReg from migen.genlib.fifo import SyncFIFO -from migen.genlib.record import Record +from migen.genlib.record import Record, layout_len from migen.genlib.misc import optree from migen.bank.description import * @@ -27,7 +27,7 @@ class ChanSync(Module, AutoCSR): ### - fifo = SyncFIFO(10, depth) + fifo = SyncFIFO(layout_len(channel_layout), depth) self.add_submodule(fifo, "pix") self.comb += [ fifo.we.eq(self.valid_i),