diff --git a/litex/boards/targets/nexys4ddr.py b/litex/boards/targets/nexys4ddr.py
index a74394805..0caba97b6 100755
--- a/litex/boards/targets/nexys4ddr.py
+++ b/litex/boards/targets/nexys4ddr.py
@@ -80,6 +80,7 @@ class BaseSoC(SoCSDRAM):
             self.submodules.ethphy = LiteEthPHYRMII(
                 clock_pads = self.platform.request("eth_clocks"),
                 pads       = self.platform.request("eth"))
+            self.add_csr("ethphy")
             self.add_ethernet(phy=self.ethphy)
 
     def add_sdcard(self):
diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 021b7a191..8bbd4d2b2 100644
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -1014,8 +1014,6 @@ class LiteXSoC(SoC):
     def add_ethernet(self, phy):
         # Imports
         from liteeth.mac import LiteEthMAC
-        # PHY
-        self.add_csr("ethphy")
         # MAC
         self.submodules.ethmac = LiteEthMAC(
             phy        = phy,