diff --git a/mibuild/platforms/lx9_microboard.py b/mibuild/platforms/lx9_microboard.py
index e259e4eb3..08d61249e 100644
--- a/mibuild/platforms/lx9_microboard.py
+++ b/mibuild/platforms/lx9_microboard.py
@@ -103,7 +103,7 @@ _io = [
 
 
 class Platform(XilinxISEPlatform):
-	bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -g SPI_buswidth:4"
+	bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g SPI_buswidth:4"
 	ise_commands = """
 promgen -w -spi -c FF -p mcs -o {build_name}.mcs -u 0 {build_name}.bit
 """
diff --git a/mibuild/platforms/usrp_b100.py b/mibuild/platforms/usrp_b100.py
index 977025559..720bed438 100644
--- a/mibuild/platforms/usrp_b100.py
+++ b/mibuild/platforms/usrp_b100.py
@@ -114,7 +114,7 @@ _io = [
 
 
 class Platform(XilinxISEPlatform):
-	bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -g UnusedPin:PullUp"
+	bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g UnusedPin:PullUp"
 	def __init__(self):
 		XilinxISEPlatform.__init__(self, "xc3s1400a-ft256-4", _io,
 			lambda p: CRG_DS(p, "clk64", "reset_n", rst_invert=True))