diff --git a/litex/soc/cores/clock/xilinx_s6.py b/litex/soc/cores/clock/xilinx_s6.py
index 396546cb4..e64a48fa8 100644
--- a/litex/soc/cores/clock/xilinx_s6.py
+++ b/litex/soc/cores/clock/xilinx_s6.py
@@ -32,9 +32,14 @@ class S6PLL(XilinxClocking):
         config = self.compute_config()
         pll_fb = Signal()
         self.params.update(
+            # Global.
             p_SIM_DEVICE     = "SPARTAN6",
             p_BANDWIDTH      = "OPTIMIZED",
             p_COMPENSATION   = "INTERNAL",
+            i_RST            = self.reset,
+            o_LOCKED         = self.locked,
+
+            # VCO.
             p_REF_JITTER     = .01, p_CLK_FEEDBACK="CLKFBOUT",
             p_CLKIN1_PERIOD  = 1e9/self.clkin_freq,
             p_CLKIN2_PERIOD  = 0.,
@@ -42,11 +47,9 @@ class S6PLL(XilinxClocking):
             p_CLKFBOUT_PHASE = 0.,
             p_DIVCLK_DIVIDE  = config["divclk_divide"],
             i_CLKINSEL       = 1,
-            i_RST            = self.reset,
             i_CLKIN1         = self.clkin,
             i_CLKFBIN        = pll_fb,
             o_CLKFBOUT       = pll_fb,
-            o_LOCKED         = self.locked,
         )
         for n, (clk, f, p, m) in sorted(self.clkouts.items()):
             self.params["p_CLKOUT{}_DIVIDE".format(n)]     = config["clkout{}_divide".format(n)]
diff --git a/litex/soc/cores/clock/xilinx_s7.py b/litex/soc/cores/clock/xilinx_s7.py
index 28263c85f..3600e7fff 100644
--- a/litex/soc/cores/clock/xilinx_s7.py
+++ b/litex/soc/cores/clock/xilinx_s7.py
@@ -31,12 +31,19 @@ class S7PLL(XilinxClocking):
         config = self.compute_config()
         pll_fb = Signal()
         self.params.update(
-            p_STARTUP_WAIT="FALSE", o_LOCKED=self.locked, i_RST=self.reset,
+            # Global.
+            p_STARTUP_WAIT = "FALSE",
+            i_RST          = self.reset,
+            o_LOCKED       = self.locked,
 
-            # VCO
-            p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=1e9/self.clkin_freq,
-            p_CLKFBOUT_MULT=config["clkfbout_mult"], p_DIVCLK_DIVIDE=config["divclk_divide"],
-            i_CLKIN1=self.clkin, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
+            # VCO.
+            p_REF_JITTER1   = 0.01,
+            p_CLKIN1_PERIOD = 1e9/self.clkin_freq,
+            p_CLKFBOUT_MULT = config["clkfbout_mult"],
+            p_DIVCLK_DIVIDE = config["divclk_divide"],
+            i_CLKIN1        = self.clkin,
+            i_CLKFBIN       = pll_fb,
+            o_CLKFBOUT      = pll_fb,
         )
         for n, (clk, f, p, m) in sorted(self.clkouts.items()):
             self.params["p_CLKOUT{}_DIVIDE".format(n)] = config["clkout{}_divide".format(n)]
@@ -71,12 +78,19 @@ class S7MMCM(XilinxClocking):
         config = self.compute_config()
         mmcm_fb = Signal()
         self.params.update(
-            p_BANDWIDTH="OPTIMIZED", o_LOCKED=self.locked, i_RST=self.reset,
+            # Global.
+            p_BANDWIDTH = "OPTIMIZED",
+            i_RST       = self.reset,
+            o_LOCKED    = self.locked,
 
-            # VCO
-            p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=1e9/self.clkin_freq,
-            p_CLKFBOUT_MULT_F=config["clkfbout_mult"], p_DIVCLK_DIVIDE=config["divclk_divide"],
-            i_CLKIN1=self.clkin, i_CLKFBIN=mmcm_fb, o_CLKFBOUT=mmcm_fb,
+            # VCO.
+            p_REF_JITTER1     = 0.01,
+            p_CLKIN1_PERIOD   = 1e9/self.clkin_freq,
+            p_CLKFBOUT_MULT_F = config["clkfbout_mult"],
+            p_DIVCLK_DIVIDE   = config["divclk_divide"],
+            i_CLKIN1          = self.clkin,
+            i_CLKFBIN         = mmcm_fb,
+            o_CLKFBOUT        = mmcm_fb,
         )
         for n, (clk, f, p, m) in sorted(self.clkouts.items()):
             if n == 0:
diff --git a/litex/soc/cores/clock/xilinx_us.py b/litex/soc/cores/clock/xilinx_us.py
index dc2ccf4dc..ffbe9b80e 100644
--- a/litex/soc/cores/clock/xilinx_us.py
+++ b/litex/soc/cores/clock/xilinx_us.py
@@ -36,12 +36,19 @@ class USPLL(XilinxClocking):
         config = self.compute_config()
         pll_fb = Signal()
         self.params.update(
-            p_STARTUP_WAIT="FALSE", o_LOCKED=self.locked, i_RST=self.reset,
+            # Global.
+            p_STARTUP_WAIT = "FALSE",
+            i_RST          = self.reset,
+            o_LOCKED       = self.locked,
 
-            # VCO
-            p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=1e9/self.clkin_freq,
-            p_CLKFBOUT_MULT=config["clkfbout_mult"], p_DIVCLK_DIVIDE=config["divclk_divide"],
-            i_CLKIN1=self.clkin, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
+            # VCO.
+            p_REF_JITTER1   = 0.01,
+            p_CLKIN1_PERIOD = 1e9/self.clkin_freq,
+            p_CLKFBOUT_MULT = config["clkfbout_mult"],
+            p_DIVCLK_DIVIDE = config["divclk_divide"],
+            i_CLKIN1        = self.clkin,
+            i_CLKFBIN       = pll_fb,
+            o_CLKFBOUT      = pll_fb,
         )
         for n, (clk, f, p, m) in sorted(self.clkouts.items()):
             self.params["p_CLKOUT{}_DIVIDE".format(n)] = config["clkout{}_divide".format(n)]
@@ -74,12 +81,19 @@ class USMMCM(XilinxClocking):
         config = self.compute_config()
         mmcm_fb = Signal()
         self.params.update(
-            p_BANDWIDTH="OPTIMIZED", o_LOCKED=self.locked, i_RST=self.reset,
+            # Global.
+            p_BANDWIDTH = "OPTIMIZED",
+            i_RST       = self.reset,
+            o_LOCKED    = self.locked,
 
-            # VCO
-            p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=1e9/self.clkin_freq,
-            p_CLKFBOUT_MULT_F=config["clkfbout_mult"], p_DIVCLK_DIVIDE=config["divclk_divide"],
-            i_CLKIN1=self.clkin, i_CLKFBIN=mmcm_fb, o_CLKFBOUT=mmcm_fb,
+            # VCO.
+            p_REF_JITTER1     = 0.01,
+            p_CLKIN1_PERIOD   = 1e9/self.clkin_freq,
+            p_CLKFBOUT_MULT_F = config["clkfbout_mult"],
+            p_DIVCLK_DIVIDE   = config["divclk_divide"],
+            i_CLKIN1          = self.clkin,
+            i_CLKFBIN         = mmcm_fb,
+            o_CLKFBOUT        = mmcm_fb,
         )
         for n, (clk, f, p, m) in sorted(self.clkouts.items()):
             if n == 0:
diff --git a/litex/soc/cores/clock/xilinx_usp.py b/litex/soc/cores/clock/xilinx_usp.py
index 7343bdee9..92e236e13 100644
--- a/litex/soc/cores/clock/xilinx_usp.py
+++ b/litex/soc/cores/clock/xilinx_usp.py
@@ -36,12 +36,19 @@ class USPPLL(XilinxClocking):
         config = self.compute_config()
         pll_fb = Signal()
         self.params.update(
-            p_STARTUP_WAIT="FALSE", o_LOCKED=self.locked, i_RST=self.reset,
+            # Global.
+            p_STARTUP_WAIT = "FALSE",
+            i_RST          = self.reset,
+            o_LOCKED       = self.locked,
 
-            # VCO
-            p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=1e9/self.clkin_freq,
-            p_CLKFBOUT_MULT=config["clkfbout_mult"], p_DIVCLK_DIVIDE=config["divclk_divide"],
-            i_CLKIN1=self.clkin, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
+            # VCO.
+            p_REF_JITTER1   = 0.01,
+            p_CLKIN1_PERIOD = 1e9/self.clkin_freq,
+            p_CLKFBOUT_MULT = config["clkfbout_mult"],
+            p_DIVCLK_DIVIDE = config["divclk_divide"],
+            i_CLKIN1        = self.clkin,
+            i_CLKFBIN       = pll_fb,
+            o_CLKFBOUT      = pll_fb,
         )
         for n, (clk, f, p, m) in sorted(self.clkouts.items()):
             self.params["p_CLKOUT{}_DIVIDE".format(n)] = config["clkout{}_divide".format(n)]
@@ -74,12 +81,19 @@ class USPMMCM(XilinxClocking):
         config = self.compute_config()
         mmcm_fb = Signal()
         self.params.update(
-            p_BANDWIDTH="OPTIMIZED", o_LOCKED=self.locked, i_RST=self.reset,
+            # Global.
+            p_BANDWIDTH = "OPTIMIZED",
+            i_RST       = self.reset,
+            o_LOCKED    = self.locked,
 
-            # VCO
-            p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=1e9/self.clkin_freq,
-            p_CLKFBOUT_MULT_F=config["clkfbout_mult"], p_DIVCLK_DIVIDE=config["divclk_divide"],
-            i_CLKIN1=self.clkin, i_CLKFBIN=mmcm_fb, o_CLKFBOUT=mmcm_fb,
+            # VCO.
+            p_REF_JITTER1     = 0.01,
+            p_CLKIN1_PERIOD   = 1e9/self.clkin_freq,
+            p_CLKFBOUT_MULT_F = config["clkfbout_mult"],
+            p_DIVCLK_DIVIDE   = config["divclk_divide"],
+            i_CLKIN1          = self.clkin,
+            i_CLKFBIN         = mmcm_fb,
+            o_CLKFBOUT        = mmcm_fb,
         )
         for n, (clk, f, p, m) in sorted(self.clkouts.items()):
             if n == 0: