From cbcd953dd77281d6d8610c009bf73146d7ca85be Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 10 Feb 2020 17:43:29 +0100 Subject: [PATCH] soc_core: use add_rom --- litex/soc/integration/soc_core.py | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index 12560f081..25a10d252 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -147,8 +147,7 @@ class SoCCore(LiteXSoC): # Add integrated ROM if integrated_rom_size: - self.submodules.rom = wishbone.SRAM(integrated_rom_size, read_only=True, init=integrated_rom_init) - self.register_rom(self.rom.bus, integrated_rom_size) + self.add_rom("rom", self.cpu.reset_address, integrated_rom_size, integrated_rom_init) # Add integrated SRAM if integrated_sram_size: