diff --git a/litex/boards/platforms/nexys_video.py b/litex/boards/platforms/nexys_video.py
index 6dbb9456f..a81b6556e 100644
--- a/litex/boards/platforms/nexys_video.py
+++ b/litex/boards/platforms/nexys_video.py
@@ -8,6 +8,10 @@ from litex.build.openocd import OpenOCD
 # IOs ----------------------------------------------------------------------------------------------
 
 _io = [
+    ("clk100", 0, Pins("R4"), IOStandard("LVCMOS33")),
+
+    ("cpu_reset", 0, Pins("G4"), IOStandard("LVCMOS15")),
+
     ("user_led", 0, Pins("T14"), IOStandard("LVCMOS25")),
     ("user_led", 1, Pins("T15"), IOStandard("LVCMOS25")),
     ("user_led", 2, Pins("T16"), IOStandard("LVCMOS25")),
@@ -46,16 +50,34 @@ _io = [
         IOStandard("LVCMOS33")
     ),
 
-    ("clk100", 0, Pins("R4"), IOStandard("LVCMOS33")),
-
-    ("cpu_reset", 0, Pins("G4"), IOStandard("LVCMOS15")),
-
     ("serial", 0,
         Subsignal("tx", Pins("AA19")),
         Subsignal("rx", Pins("V18")),
         IOStandard("LVCMOS33"),
     ),
 
+    ("usb_fifo", 0, # Can be used when FT2232H's Channel A configured to ASYNC FIFO 245 mode
+        Subsignal("data",  Pins("U20 P14 P15 U17 R17 P16 R18 N14")),
+        Subsignal("rxf_n", Pins("N17")),
+        Subsignal("txe_n", Pins("Y19")),
+        Subsignal("rd_n",  Pins("P19")),
+        Subsignal("wr_n",  Pins("R19")),
+        Subsignal("siwua", Pins("P17")),
+        Subsignal("oe_n",  Pins("V17")),
+        Misc("SLEW=FAST"),
+        Drive(8),
+        IOStandard("LVCMOS33"),
+    ),
+
+    ("sdcard", 0,
+        Subsignal("rst",  Pins("V20"),             Misc("PULLUP True")),
+        Subsignal("data", Pins("V19 T21 T20 U18"), Misc("PULLUP True")),
+        Subsignal("cmd",  Pins("W20"),             Misc("PULLUP True")),
+        Subsignal("clk",  Pins("W19")),
+        Misc("SLEW=FAST"),
+        IOStandard("LVCMOS33"),
+    ),
+
     ("ddram", 0,
         Subsignal("a", Pins(
             "M2 M5 M3 M1 L6 P1 N3 N2",
@@ -232,7 +254,7 @@ class Platform(XilinxPlatform):
         self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 35]")
 
     def create_programmer(self):
-        return OpenOCD("openocd_xc7_ft2232.cfg", "bscan_spi_xc7a200t.bit")
+        return OpenOCD("openocd_nexys_video.cfg", "bscan_spi_xc7a200t.bit")
 
     def do_finalize(self, fragment):
         XilinxPlatform.do_finalize(self, fragment)